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SDRAM控制器源码,内含完整的控制器verilog源代码和测试代码,超值哈。...
SDRAM控制器源码,内含完整的控制器verilog源代码和测试代码,超值哈。-This readme file for the SDR SDRAM Controller includes information that was not
incorporated into the SDR SDRAM Controller White Paper v1.1.
- 2023-07-19 13:10:03下载
- 积分:1
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fpga_dk_ps2_vga
ps2 vga interface in vhdl code
- 2011-11-08 11:09:35下载
- 积分:1
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用verilog语言编写的步进电机加减速控制算法 Motion_control
用verilog语言编写的步进电机加减速控制算法,可选择梯形曲线或S型曲线算法(Verilog language stepper motor acceleration and deceleration control algorithm, you can choose the trapezoidal curve or S-curve algorithm)
- 2021-03-19 15:39:19下载
- 积分:1
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FPGA
基于FPGA实现的一种新型数字锁相环-FPGA-based realization of a new type of digital phase-locked loop
- 2023-01-20 11:30:04下载
- 积分:1
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src
v6 1x 3.125G rapidio协议工程代码(xilinx v6 rapidio data transmission protocol Practical project application engineering code)
- 2018-03-20 23:28:49下载
- 积分:1
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VHDL实用教程(潘松),非常经典讲解VHDL语言,包含基本语法及实例。...
VHDL实用教程(潘松),非常经典讲解VHDL语言,包含基本语法及实例。-VHDL Practical Guide (Pan Song), is a classic on the VHDL language, including basic grammar and examples.
- 2022-08-07 10:44:16下载
- 积分:1
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mux21a
在VHDL结构体中用于描述逻辑功能和电路结构的语句分为顺序语句和并行语句两部分,顺序语句的执行方式十分类似于普通软件语言的程序执行方式,都是按照语句的前后排列方式顺序执行的。(VHDL structure in the body used to describe the logic function and circuit structure of the order of statements and expressions are divided into two parts in parallel statement, modalities for the implementation of the order of statement is very similar to ordinary language software program implementation, are in accordance with the statements before and after the arrangement of the order implementation.)
- 2008-12-24 18:25:20下载
- 积分:1
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pld_Tetris
基于FPGA cyclone III EP3C16F484C6的俄罗斯方块游戏。实现双人进行,屏幕倒置,分数显示,vga接口,键盘接口等功能(Tetris game based on FPGA cyclone III EP3C16F484C6 with functions including double players, screen upside down, score, vga and keyboard interface.)
- 2020-11-06 12:39:49下载
- 积分:1
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05_fifo_test
说明: FIFO: First in, First out 代表先进的数据先出,后进的数据后出。Xilinx 在 VIVADO 里为我们已经提供了 FIFO 的 IP 核, 我们只需通过 IP 核例化一个 FIFO,根据 FIFO 的读写时序来写入和读取FIFO 中存储的数据。(FIFO: first in, first out represents the first out of advanced data, and the last in data is the last out. Xilinx has provided us with the IP core of FIFO in vivado. We only need to instantiate a FIFO through the IP core, and write and read the data stored in FIFO according to the FIFO read-write timing.)
- 2021-04-08 22:19:20下载
- 积分:1
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ComChange-12061629
说明: 并行读写14路串口数据,数据被写入FIFO,在收到读写信号后,SPI发送数据出去(Parallel read and write 14 serial port data, SPI send data)
- 2019-03-13 01:38:44下载
- 积分:1