由VHDL 语言实现的DA0832器利用的是QUARTUES环境已经得到验证

说明：  bt1120设计方案，描述了具体的方案设计以及整体的架构设计(Bt1120 design scheme, describes the specific scheme design and the overall architectural design)

ARM7系统IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。(ARM7 System IP Core VHDL language source code, the need for the development environment is QUARTUS II 6.0.)

FPGA设计流程指南 介绍基本的设计方法-FPGA Design Process Manual

DS18b20 temperature sensor vhdl code

多倍（次）分频器 请注意: 本例的各个源描述的编译顺序应该是: 52_divider.vhd 52_divider_stim.vhd-Times (times) divider Please note: This case is described in various sources to compile the order should be: 52_divider.vhd 52_divider_stim.vhd

7段数码显示译码器-seven of the digital display decoder

tle转换为六根数的c++源代码，英文原版代码，测试可用(tle converted to six the number of c++ source code, the English original code, test available)

4tap FIR filter in verilog code

verilog写的频率计程序的计数模块,-Verilog written procedures for counting frequency meter module,

基于Verilog HDL的数字电压表的程序-Verilog HDL-based procedures for the digital voltmeter