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是用VHDL语言写的对A/D转换模块的控制程序,希望对大家有帮助。...
是用VHDL语言写的对A/D转换模块的控制程序,希望对大家有帮助。-VHDL language is used on the A/D conversion module control procedures, in the hope that everyone has to help.
- 2023-05-25 06:40:03下载
- 积分:1
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A_PUF_Design
基于fpga的物理不可克隆函数(PUF)模块的实现(A PUF Design for Secure FPGA-Based Embedded Systems)
- 2014-06-28 15:37:44下载
- 积分:1
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sp605_BRD_rdf0033_13.2_c
spartan605评估板测试代码。xilinx官方资料(spartan605 uation board test code)
- 2014-12-23 22:27:45下载
- 积分:1
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Experiment_1_Xilinx
很不错的FPGA入门级实验指导书,按照实验的知道,能够学会使用ISE仿真简单的流水灯。教程较为详细,从硬件连接到代码编写都做了详细指导,适合新手入门。(Very good entry-level FPGA experimental guide books, according to the experiment know, be able to learn to use the ISE Simulator simple water lights. Tutorial in detail, the hardware connected to the coding have done a detailed guide for beginners.)
- 2016-09-16 23:07:26下载
- 积分:1
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PIC16系列单片机的Verilog描述的完整性
完整的PIC16系列单片机verilog描述-A complete description of PIC16 series of microcontrollers verilog
- 2022-07-23 07:13:49下载
- 积分:1
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使用VHDL实现锁相环,是个学习VHDL的好例子,与众分享
使用VHDL实现锁相环,是个学习VHDL的好例子,与众分享-PLL using VHDL, VHDL is learning a good example, sharing with the public
- 2023-08-12 00:15:02下载
- 积分:1
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8051_VHDL
mc8051代码,里面功能齐全,调试方便(mc8051 code, inside a full-featured, easy debugging)
- 2008-03-28 14:54:19下载
- 积分:1
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dvb_s2_ldpc_decoder_latest.tar
LDPC COded OFDM System
- 2013-02-09 21:41:33下载
- 积分:1
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ADC_Data_Recv_Module
接收机测试输入信号,
生成正余弦波,采样率、频率、幅度、相位可调节
并将生成的数据进行输出
压缩包包括Verilog代码、testbench代码、word文档
matlab仿真代码(The receiver tests the input signal,
Generation of positive cosine wave, sampling rate, frequency, amplitude, phase can be adjusted
And output the generated data
The compressed package includes the Verilog code, the testbench code
Matlab simulation code)
- 2017-12-08 17:56:02下载
- 积分:1
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Comparator for Quartus
Comparator for Quartus
- 2022-06-21 21:12:14下载
- 积分:1