Verilog entry basis, as well as introduce a simple programming, verilog in recen...

基于Montgoery 算法的RSA,FPGA verilog 实现，有测试文件(Based on Montgoery algorithm for RSA,FPGA verilog implementation，bench file)

Use full for knowing board details while making projects on FPGA and matlab simulations

适用于FPGA的SOPC方面的元器件添加，如COMPNENT-Applicable to FPGA-SOPC area to add components, such as COMPNENT

地铁售票系统，基于VHDL，可实现站点设置，站点选择，选择购票数量，找零等一系列功能。-Metro ticketing system, based on VHDL, allows site settings, site selection, choose the number of tickets, Keep the change and a series of functions.

定时器加数码管显示源码，以及test bench测试模块源码，经modelsim仿真结果正确(Timer plus digital display source code, and test bench test module source code, by modelsim simulation results are correct)

本系统用于GPS中频部分的窄带滤波（AD后的数据经过LMS滤波后去掉窄带干扰，可以抑制20dB以上的干扰）(this system can be imply to anti-narrowband-jamming for GPS IF signal, it can degrade 20dB narrowband jamming)

说明：  HDMI IP的verilog实现，vivado平台生成的IP核(Verilog implementation of HDMI IP)

maxplus2为开发环境 vhdl编写的 扫描 程序-maxplus2 VHDL development environment for the preparation of a scanning program

PCIe demo sample code

this is a sum for 2 digit numbers