A VHDL design with the use of powerful 32

预失真算法中，包络解波部分的verilog代码，有部分错误(envelope calculation of DPD algorithm ，verilong HDL language)

用FPGA中的三速以太网来实现UDP通信，功能强大(With a triple-speed Ethernet in the FPGA to implement UDP communication, powerful)

JOP内核字节码获取，很难找的东东，呕血之作-JOP core byte code access, it is difficult to find the price. Zhi for hematemesis

由8 位加法器构成的以时序方式设计的8 位乘法器，采用逐项移位相加的方 法来实现相乘的VHDL程序代码。包含几个小模块和一个顶层设计文件，运行可用。(an 8 bit multiplier combined with 8 bit adder using a design by way of timing,and it use a way of Itemized shift to implement the multiply.It include some little module and a top level design document.)

Camera AR0134详细的寄存器配置，以及配置顺序，可以用来初始化摄像头(Camera AR0134 detailed register configuration sequence )

Variable Reduction Testbench通过对变量进行相关性分析来实现减少变量的目的。-Variable Reduction Testbench is a MATLAB module that allows the application of several methods for variable reduction based on correlation analysis

说明：  基于OV7670采集，SDRAM缓存，sobel处理，VGA显示的工程，内有全部代码，基于QUARTUS开发板实现。 FPGA 边缘检测(Based on OV7670 acquisition, SDRAM cache, sobel processing, VGA display project, with all the code, based on QUARTUS development board. FPGA edge detection)

北斗定位系统卫星下行信号的基带处理部分——基于FPGA的的直接序列扩频发射机的设计与仿真。，已通过测试。 (Beidou positioning system satellite downlink signal baseband part- based on the design and simulation of the FPGA direct sequence spread spectrum transmitter. , Has been tested.)

xilinx xc9572 cpld 实现的伺服电机控制器，电机控制输出，和增量编码器读取。-Xilinx xc9572 cpld achieve servo motor controller, motor control output, Incremental encoder and the reader.

说明：  artix 7系列 fpga mig ddr3应用教程(Artix 7 Series FPGA MIG DDR3 Application Tutorial)