counter (2)
于 2017-07-18 发布
文件大小:1KB
0 218
下载积分: 1
下载次数: 1
代码说明：
This tutorial introduce VHDL code for clock pulse and 4-bit counter. With four bits, the counter count from 0 to 15. The timing of the counter is controlled by a clock signal. There will be a clear signal which can reset the counter value.
下载说明：请别用迅雷下载，失败请重下，重下不扣分！
发表评论
