基于FPGA的fir滤波器的代码

键盘按键消抖,短时间内的摁键键值采集，在规定时间内，如果存在按键的上升沿和下降沿，不予以采集，超过该时间，则采集为该键当前状态值

FIR滤波器：自定滤波器的类型（低通，高通或带通）、设计指标（通带截止频率、通带波纹、阻带截止频率、阻带衰减） 1、根据指标选择合适的窗函数，用窗口设计法设计符合指标的FIR滤波器；并验证其性能是否满足预定指标。 (FIR filters: Custom filter types (low pass, high pass or band-pass), design specifications (passband cutoff frequency, passband ripple, stopband cutoff frequency, stopband attenuation) 1, according to indicators choose the right window function, using the window design method of FIR filter designed to meet the targets and verify that its performance meets the set targets.)

使用verilog语言进行编码 完成mdio接口访问phy8201芯片的功能(Use verilog language to encode the mdio interface to access the function of phy8201 chip)

数字频率测量器，脉宽测量器。可测量多种频率波形的脉宽。(Digital frequency measurement device, pulse width measurement device. Measurement of the waveform of frequency pulse width)

2ask调制与解调的源代码，经过测试可用(2ask modulation and demodulation source code is available, tested)

说明：  用verilog编写的LVDS接口驱动程序，采用IOSERDES技术实现，经过Spartan6 FPGA调试验证，有完整的工程。(The LVDS interface driver written in verilog is implemented using IOSERDES technology. After Spartan6 FPGA debugging and verification, there is a complete project.)

Introduction to learn laboratry with altera quartus II 9.1

this is the vhdl code for the arithmetic logic unit.enjoy!

四通道DDS信号发生器，很好用的代码，大家一起分享(Four-channel DDS signal generator)

FPGA之间通信，或者FPGA和DSP之间通信的接口协议，用verilog代码编写，验证可用！