一款商用ADC的verilog

本实验将采用双通道 12bit AD 9226在开发板上实现数据采集和模数 转换的功能(This experiment will use dual channel 12bit AD 9226 to realize data acquisition and module on the development board. The function of conversion)

Nexys-4-DDR-XADC 开发板demo(Nexys-4-DDR-XADC e.v. Board demo)

矩阵键盘控制的FPGA，verilog语言实现，包括rtl，ucf,以及testbench的详尽代码(Exhaustive code matrix keyboard control FPGA, Verilog language, including the rtl, ucf, and testbench)

这是自适应滤波器，使用verilog代码来编写的，已通过了仿真，效果很好。希望能给大家好好分享！(This adaptive filter verilog code to write, through a simulation, with good results. I hope to give a good share!)

说明：  38译码器，D触发器，全加器，计数器，抢答器，优先编码器，111序列检测器，并行输入转串行输出(poor English. 38 decoder, D trigger, full adder, counter, scrambler, priority encoder, 111 sequence detector, parallel input to serial output)

基于FPGA的Sobel边缘检测算法的实现与仿真。此程序提供算法的verliog实现。(Implementation and Simulation of Sobel edge detection algorithm based on FPGA. This program provides the verliog implementation of the algorithm.)

sd卡读写，仿真模型，testbanch测试文件(sdcard read write and sdcard model)

FPGA实现乒乓球游戏 代码及仿真 VGA实现(FPGA realizes table tennis game code and simulation VGA implementation)

说明：  基于FPGA的任意波形发生器DDS,verilog编写，正常使用(Arbitrary waveform generator DDS based on FPGA)

SDRAM控制器源码，内含完整的控制器verilog源代码和测试代码，超值哈。(This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1.)