Verilog ADPLL文件与测试

QC LDPC的编码译码 代码与论文配套 是研究生毕设 可运行 代码风格优秀(QC LDPC Coding and Decoding Code and Paper Matching are Excellent Style of Running Code for Graduate Students)

伽罗华域的乘法器的设计，使用有限域设计乘法器(Galois field multiplier design, the use of finite field multiplier design)

说明：  在FPGA实验操作系统实现ASK,FSK,PSK的调制解调，基带信号由M序列发生器产生，经过AD模块在示波器上进行显示，精油DA模块在同一块实验板上进行解调操作，生成信号控制LED灯的亮灭，并与调制输出信号在示波器上同时展示，并进行对比。基带信号为3MHz。(In the FPGA operating system experiment implementation ASK, FSK, PSK modulation and demodulation of the baseband signal generated by the M sequence generator, through the AD module on the oscilloscope display module, oil DA demodulation operation in the same block experiment board, the signal generation control LED lights off, and the modulated output signal displayed on the oscilloscope at the same time, and compared.)

超前进位加法器得VHDL实现小点资料代码(CLA was a small point of information VHDL code)

This code for countor . it is design in verilog HDL.

Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model -Turbo Decoder Release 0.3* Double binary, DVB-RCS code* Soft Output Viterbi Algorithm* M yHDL cycle/bit accurate model* Synthesizable VHDL model

大名鼎鼎的Synopsys公司出的8051IP Core VHDL语言编写，能被keilC51支持-famous Synopsys Core 8051IP the VHDL language, can be supported keilC51

ADDER USING VERILOG ADDER WITH VERILOG VERILOG ADDER

matlab 程序 伪随机码的捕获,我传的都是这方面的资料！(failed to translate)

uart通信的Verilog实现,包含rx tx 以及testbench(Verilog implemention of UART telecommunicate)