直接序列扩频通信系统VHDL仿真

Verilog HDL for Half Adder, Full Subtractor, Half Subtractor and 2x4 decoder.

说明：  华为 Verilog基本电路设计指导书--本文列举了大量的基本电路的Verilog HDL 代码，使初学者能够迅速熟悉基本的HDL 建模；同时也列举了一些常用电路的代码(Huawei Verilog basic circuit design instruction)

这个是一个基于FPGA的数字图像的整数DCT变换程序，程序高性能地实现了2维DCT变换。-This is an FPGA-based digital image of the integer DCT transform process and procedures to achieve high-performance 2-D DCT transform.

说明：  关于地铁售票的一些功能 基于自动买票的VHDL设计程序 比较经典(Subway ticket on some of the features of the VHDL-based auto-buying classic design procedure)

网上流传的用来实现FPGA驱动VGA，从而实现一个pingpong小游戏的源码，实测可用。(a program embedded in a FPGA in order to drive the VGA and realize a little game named pingpong. tested.)

说明：  APPCM算法和AD/DA芯片驱动在CPLD中的实现，已在实际硬件中测试OK，quartus2环境(APPCM algorithm and AD/DA chip in the drive to achieve in the CPLD has been tested in actual hardware OK, quartus2 environment)

this come from alter ,you can look and find it on line about h263.

SRAM简单测试，测试其性能及其速度，判断SRAM是否可用(Test its performance and speed to determine if SRAM is available)

verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.

只需要FPGA两个通用管脚，就可以实现FPGA与PC机进行以太网通信！！如果你有ALTERA_DE1的开发板，可以直接下再看效果，用其他板子就要重新分配一下管脚，推荐使用电流输出。-Only two general-purpose FPGA pins, you can realize FPGA and Ethernet PC machine! ! If you have ALTERA_DE1 development board, you can look under the direct effect, with other board you will need to reconsider the distribution of pins, recommended the use of current output.