VGA FPGA时序仿真，仿真的PS / 2键盘接口VHDL源C.

非常好的SDRAM Controller 设计文档。工程必备-SDRAM Controller Design of a very good document. Works required

说明：  通过监测工作状态实现带有IIC通讯功能的数据发送接收(to implement the sending and receiving data function of iic communication )

these files are written in verilog but i am uploading in text format

代码风格非常好，容易看懂，移植性高

数控分频器的设计数控分频器的功能就是当在输入端给定不同输入数据时，将对输入的时钟信号有不同的分频比，数控分频器就是用计数值可并行预置的加法计数器设计完成的，方法是将计数溢出位与预置数加载输入信号相接即可。-NC NC divider divider design of its function is when the input given different input data, input the clock signal will have different sub-frequency ratio, NC prescaler value can be used include parallel preset counter adder design is completed, the method is to count the number of overflow bit with preset load to the input signal phase.

说明：  CPU设计，包含基本的指令集，能执行简单的程序。考虑了CPU，寄存器，存储器和指令集之间的关系。即读写寄存器，读写存储器和执行指令。(CPU design, including basic instruction set, to execute a simple program. Consider the CPU, registers, memory, and the relationship between instruction sets. That read and write registers, read and write memory and execution.)

用VHDL语言仿真音乐设计 用VHDL语言仿真音乐设计-Simulation using VHDL language music design music design simulation VHDL language

说明：  【实例简介】用Verilog实现uart串口协议，波特率可选9600、19200、38400、115200。8位数据为，1位校验位，1位停止位。 【实例截图】 【核心代码】核心代码包括TX，RX，Baud，FIFO([example introduction] UART serial port protocol is implemented with Verilog, and the baud rate can be 9600, 19200, 38400, 115200. 8-bit data, 1 bit check bit, 1 stop bit. [example screenshot] [core code] the core code includes TX, Rx, baud and FIFO)

cpld/fpga常用加法器设计的verilog程序-cpld/fpga common adder Verilog design procedures

如何用VHDL语言对时钟进行分频以达到计数目的(how to achive counting by VHDL Language)