Xilinx FPGA moving data across asynchronous clock boundaries

北大verilog课件，数字集成电路设计入门，从HDL到版图-North Verilog courseware, digital IC design entry, from HDL to the map

中值滤波算法的verilog实现，可用于相关算法在基于FPGA的嵌入式图像处理系统中。(Median filtering algorithm verilog realization available FPGA-based embedded image processing system.)

Verilog 下脉冲发生器的源代码，可用于模拟三相交流电过零点，主要用于调试一些类似SVC（无功补偿）控制器的一些算法-Pulse generator under the Verilog source code, can be used to simulate three-phase alternating current zero-crossing point, mainly for debugging similar SVC (reactive power compensation) controller of a number of algorithms

EDK tutorial 1 ----------------

dual port ram control (dual port ram control dual port ram control dual port ram control)

交织和解交织模块，采用矩阵交织方式，且有两套并行存储器，可以实现连续数据流操作，不会有数据滞留和丢失-Intertwined intertwined reconciliation module, interwoven matrix approach, and has two sets of parallel memory, you can realize continuous data stream operations, will not have data retention and loss

交通灯控制系统VHDL源码，用VHDL语言、MAXPLUS2环境设计实现(VHDL core)

一个非常好的dc使用书籍 一个非常好的dc使用书籍-Dc to use a very good book a very good use of books dc

说明：  这是一个关于OQPSK的Matlab程序 这是一个关于OQPSK的Matlab程序 (This is a OQPSK the Matlab program is a program of OQPSK in Matlab)

51数字钟带各种扩展年，月，日等并且可预置。用汇编语言写的(51 digital clock with extended assembly language)