Xilinx FPGA moving data across asynchronous clock boundaries

Learning Verilog Chinese Version Part 8

说明：  xilinx 平台的SPI从接口实现源码，供参考学习(used xilinx,slave-spi interface.)

涉及到常用的模块，参数可配置，可以很方便的集成到应用中(Related to commonly used modules, parameters can be configured, can be easily integrated into applications)

verilog vga 图像处理(verilog vga)

说明：  本例的源描述超过了演示版限制的300行, 如果您需要对其进行编译与模拟,请与北京理工大学 ASIC研究所联系,获取Talent系统的完全版本. 联系方法: 电话:010-68912434 (The source described in this case than the demo version of the 300 line limit, if you need to be compiled with the simulation, please contact ASIC Institute of Beijing Institute of Technology to obtain the complete version of Talent system. Contact: Tel :010-68912434)

VHDL教程及源码,是新手入门的不二选择!-VHDL Tutorial and source code is the only option, beginners!

利用数字电路知识，进行二十四小时计时，并有闹钟与蜂鸣器功能-Knowledge of the use of digital circuits, the 24 hours time, and there is an alarm clock function and buzzer

移位乘法器的输入为两个4位操作数a和b，启动乘法器由stb控制，clk信号提供系统定时。乘法器的结果为8位信号result,乘法结束后置信号done为1. 乘法算法采用原码移位乘法，即对两个操作数进行逐位的移位相加，迭代4次后输出结果。具体算法： 1. 被乘数和乘数的高位补0，扩展成8位。 2. 乘法依次向右移位，并检查其最低位，如果为1，则将被乘数和部分和相加，然后将被乘数向左移位；如果为0，则仅仅将被乘数向左移位。移位时，被乘数的低端和乘数的高端均移入0. 3. 当乘数变成全0后，乘法结束。 -err

具有桥式结构的传感器很多，如利用应变原理、磁电阻原理和其他变电阻原理的传感器，可以实现对压力、位移、加速度、磁场等物理量的测试。这种结构的差分输出可以增加灵敏度，也有一定抵消外加干扰的能力。而且有的虽不是差分输出，比如电阻分压式的输出，可以认为是“半桥”，我们还可以人为的加上另一半，即加上一对精密电阻和一个电位器组成另一个分压电路，形成差分输出。每次调节电位器使差分输出为0，抵消零磁电压。-Bridge structure with many sensors, such as the use of contingency theory, the principle of magneto-resistance and other variable resistance sensor principle can be achieved on the pressure, displacement, acceleration, magnetic field, such as physical tests. The structure of the differential output can increase sensitivity, but also have some ability to offset the additional interference. And some is not a differential output, such as pressure resistance of the output type, you can think is

有限状态机工作原理、设计方法、步骤等精要说明(Finite state machine working principle, design method, such as Essentials of steps to explain)