Xilinx FPGA moving data across asynchronous clock boundaries

429总线通过FPGA直接实现发送程序,通过Verilog实现(send 429 message by Verilog and FPGA )

wimax ofdm系统评估代码 wimax ofdm system code 很有参考价值(wimax ofdm system code)

此代码实现4人表决功能，4人中有三人同意即为通过。(Four voting)

该程序实现多项式分数延迟（farrow）的设计。(The program polynomial fractional delay (farrow) design.)

说明：  ADDER USING VERILOG ADDER WITH VERILOG VERILOG ADDER

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像形态学部分,腐蚀,膨胀,细化算法(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image morphology section, corrosion, swelling, thinning algorithm)

AHB 总线slave verilog实现(Implementation of AHB bus)

vhdl source code for 8 bit datapath logic

基于单片机显示原理的IO和LED显示原理(Based on the principle of IO chip and LED display shows the principle)

使用verilog语言，滚动显示“verilog”字符串程序代码及相关说明(Using verilog language, scrolling display " verilog" string code and instructions)