一个16位cpu的vhdl代码。具体内容我也不清楚，自己慢慢研究吧...

正弦波在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-sine wave in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim

实现了MASH111功能，输入位数可编程(MASH 1-1-1, delta-sigma , input bits are programmable)

二进制除法器，采用移位相减的方法实现，位数可调-The source code of a divider

cordic的verilog程序 用ＦＰＧＡ实现-CORDIC FPGA using the Verilog procedures realize

PLD与8051接口的参考设计 Xilinx提供的verilog源代码-PLD 8051 interface with the Xilinx Reference Design for the Verilog source code

说明：  潘松那本书上用vhdl语言描述的16位并入并处加法器(Pan book vhdl language used to describe the 16-bit adder into his)

实现二项混合式步进电机的驱动，和步进电机的细分程序。(The driving of binomial hybrid stepper motor and the subdivision program of stepper motor are realized.)

使用Verilog语言编程，在Quartus ii 上实现的误码检测装置，并通过单片机将误码结果显示在LCD上。本代码具有一定的工程实践价值。(Using the Verilog language programming, implemented on the Quartus ii error detection device, and the result of errors by the microcontroller on the LCD display. The code has some value engineering practice.)

Three-input Majority Voter -- The entity declaration is followed by three alternative architectures which achieve the same functionality in different ways. -Three-input Majority Voter -- The entity declaration is followed by three alternative architectures which achieve the same functionality in different ways.

VHDL实现国家SM4加密算法（ECB）模式 (VHDL to achieve national SM4 encryption algorithm (ECB) mode)