这是一个测试键盘的代码

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设计了一个异步时钟域间进行通行的模块，并采用Modelsim进行仿真验证，仿真结果满足预期的目的。-Designed an asynchronous clock domains between the passage of the module, and use Modelsim for simulation, the simulation results meet the intended purpose.

vhdl code for GIF Image Viewer

i have coding for verilogHDL and VHDL. so please i want know that coding..

设计一个具有同步置1，异步清零的D触发器。 设计一个类似74LS160的计数器(Design an D trigger with synchronous reset 1 and asynchronous reset. Design a counter like 74LS160.)

Verilog学习例程EP2C5，内有跑马灯等18个程序(Verilog learning routines EP2C5, marquees and other 18 programs)

four bit counter verlog source code for veriwell including test bench

彩灯控制器 vhdl语言开发 eda实验-Lantern controller vhdl language test eda

1.JESD204B协议 2.Xilinx的JESD204B phy 核手册 3.Xilinx的JESD204B rx_tx 核手册7.1 4.Xilinx的JESD204B rx_tx 核手册7.2 5.verilog实现串口发送(1.JESD204B protocol 2.Xilinx JESD204B PHY core manual 3.Xilinx JESD204B rx_tx core manual 7.1 4.Xilinx JESD204B rx_tx core manual 7.2 5.verilog to achieve serial transmission)

sender的verilog 利用fpga实现-sender using the Verilog FPGA realize