UART模块用VHDL。

The Date prototype object is itself a Date object (its [[Class]] is "Date") whose value is NaN.

运用vhdl程序设计语言进行ppm设计，ppm 设计在vhdl语言中非常常用，运用已经越来越广泛。-use vhdl program design language ppm design, vhdl ppm design in a very common language, has become increasingly widespread use.

说明：  Multiplexer 4 to 1 on Modelsim

Xilinx FPGA make 50 smaller-Xilinx FPGA make 50 smaller

一个走马灯的程序,可以按照要求一个一个往后面按顺序点亮(A program for the lantern can be lit one by one according to the requirements.)

VHDL_COUNTING 0_9_LED 7 段 (ĐẾM 0 ĐẾN 9 HIỂN THỊ LED 7 ĐOẠN BẰNG NGÔN NGỮ VHDL)

基于verilog的1588V2协议的fpga实现，目前项目通用代码，供大家参考(Based on verilog 1588 v2 fpga implementation of the agreement, the project general code, for your reference)

这是一个最最常用的用vhdl写的状态机，几乎哪儿都用得到(a very good state machine)

vhdl语言和verilog语言转换工具 能很容易的实现两种语言的相互转换-verilog language vhdl language and conversion tools can easily achieve the conversion between two languages

i2c配置SAA7113，非常有用的程序，做视频采集类必看(i2c configure SAA7113)