登录
首页 » VHDL » vhdl语言和verilog语言转换工具 能很容易的实现两种语言的相互转换...

vhdl语言和verilog语言转换工具 能很容易的实现两种语言的相互转换...

于 2022-08-16 发布 文件大小:3.78 MB
0 139
下载积分: 2 下载次数: 1

代码说明:

vhdl语言和verilog语言转换工具 能很容易的实现两种语言的相互转换-verilog language vhdl language and conversion tools can easily achieve the conversion between two languages

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • ug835-vivado-tcl-commands
    说明:  Vivado是Xilinx最新的FPGA设计工具,支持7系列以后的FPGA及Zynq 7000的开发。与之前的ISE设计套件相比,Vivado可以说是全新设计的。无论从界面、设置、算法,还是从对使用者思路的要求,都是全新的。看在Vivado上,Tcl已经成为唯一支持的脚本,此文件是vivado是tcl命令的集合。(Vivado is Xilinx's latest FPGA design tool that supports development of FPGAs and Zynq 7000s in the 7 series and beyond. Compared with the previous ISE design suite, Vivado can be said that the new design. No matter from the interface, settings, algorithms, or from the user ideas, are new. Look at Vivado, Tcl has become the only supported script, this file is vivado tcl command collection.)
    2020-10-26 22:50:00下载
    积分:1
  • 在ise10.1.3 Xilinx PicoBlaze的应用开发。
    Xilinx PicoBlaze application developed in ISE10.1.3.
    2023-07-28 07:25:03下载
    积分:1
  • VHDL实现led灯的动态扫描,主要对CLK进行分频
    VHDL实现led灯的动态扫描,主要对CLK进行分频-VHDL realization led lamp dynamic scan, the main points of the CLK to the frequency
    2023-03-21 08:35:04下载
    积分:1
  • 用verilog HDL语言,通过一个4位移位寄存器实现一个信号转化为HDB3码并进行测试...
    用verilog HDL语言,通过一个4位移位寄存器实现一个信号转化为HDB3码并进行测试 -Using verilog HDL language, through a 4-bit shift register realization of a signal into HDB3 code and test
    2023-05-23 03:15:03下载
    积分:1
  • counter
    设计一个十进制计数器模块,输入端口包括 reset、up_enable 和 clk,输出端口为 count 和 bcd,当 reset 有效时(低电平),bcd 和 count 输出清零,当 up_enable 有效时(高电 平),计数模块开始计数(clk 脉冲数),bcd 为计数输出,当计数为 9 时,count 输出一 个脉冲(一个 clk周期的高电平,时间上与“bcd=9”时对齐)(Design of a decimal counter module, input port, including the reset up_enable clk, output port for the count and bcd, when reset is active (low), the bcd and count output cleared up_enable active (high), count module starts counting the (the CLK pulse number), the BCD count output when the count 9, the count output of the high level, the time of a pulse (a clk cycle with " bcd = 9" when aligned))
    2013-04-13 19:53:29下载
    积分:1
  • dianzhen
    基于FPGA的16*16点阵中文LED显示,另带有几个简单的中文汉字的点阵数据。(FPGA-based 16* 16 dot matrix Chinese LED display, and the other with a few simple lattice data Chinese characters.)
    2014-05-30 21:47:37下载
    积分:1
  • 82 VHDL, verilog test case, involving a variety of grammatical rules. which is...
    包括VHDL、verilog在内的各种设计实例,是学习硬件描述语言的帮手。共有82个实验例子,涉及各种语法规则。-82 VHDL, verilog test case, involving a variety of grammatical rules. which is you learn the HDL language helper.
    2023-06-06 10:15:04下载
    积分:1
  • ethernet_mac-master
    说明:  ethernet mac vhdl verilog basic
    2019-03-30 15:47:25下载
    积分:1
  • 这是DES的Verilog源代码(数据加密标准)是用来在N.
    This is verilog source code for DES(Data Encryption standard) which is used in network security.
    2022-04-21 02:32:09下载
    积分:1
  • 1024point-fft--using-verilog-hdl
    1024点快速傅里叶变换,使用verilog hdl硬件描述语言(1024point FFT,using verilog hdl)
    2013-03-09 10:54:42下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载