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pipelined_fft_64_128_256
用verilog实现64点,128点,256点的fft(64 points, 128 points, and 256 points FFT are implemented with Verilog)
- 2018-05-11 14:57:35下载
- 积分:1
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Veriolg HDL的D触发器
D触发器程序,适合初学者使用和学习,Verilog hdl语言的,使用Xillinx公司的芯片。
- 2022-10-29 12:45:03下载
- 积分:1
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nios_ruanhe_spi_3
这是我自己写的一个摄像头数据存储SD卡程序,quartus的verilog编写,摄像头采用自己添加的外设接口,数据采用dma采集,SD用的是软件自带的SPI内核以及znFAT的文件系统。帧率我没有测,有兴趣的可以测测,初学者可以参考学习,写的代码有点乱,如果有不懂的可以和联系。(This is what I wrote it myself a camera, SD card data storage program, quartus the verilog write, add their own camera with peripheral interfaces, data acquisition using dma, SD with the software that comes with SPI znFAT kernel and file system. I did not measure the frame rate, are interested can Cece, beginners can refer to the study, wrote the code a bit messy, if there do not understand can contact)
- 2015-09-18 11:39:07下载
- 积分:1
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ps2_lcd
此代码能够使得键盘控制液晶,实时的进行书写,按下Backspace清屏(This code enables the keyboard to control the LCD, in real-time writing, press Backspace clear the screen)
- 2013-01-27 11:04:40下载
- 积分:1
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verlog通过FPGA实现数字钟
verlog通过FPGA实现数字钟,包含时间计数,秒表和闹钟等功能
- 2022-03-14 07:30:03下载
- 积分:1
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dividefrequency
如何用VHDL语言对时钟进行分频以达到计数目的(how to achive counting by VHDL Language)
- 2009-02-13 15:45:38下载
- 积分:1
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AHB总线代码
APB主要用于低带宽的周边外设之间的连接,例如UART、1284等,它的总线架构不像AHB支持多个主模块,在APB里面唯一的主模块就是APB 桥。其特性包括:两个时钟周期传输;无需等待周期和回应信号;控制逻辑简单,只有四个控制信号。
- 2022-01-29 03:34:40下载
- 积分:1
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SRAM 简单测试
SRAM简单测试,测试其性能及其速度,判断SRAM是否可用(Test its performance and speed to determine if SRAM is available)
- 2020-07-10 09:58:55下载
- 积分:1
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dianziqingsheji
实现拟想要的音乐,基于at89s51单片机的电子琴设计!(To achieve the desired music to be based at89s51 keyboard microcontroller design!)
- 2010-05-19 14:01:34下载
- 积分:1
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ADC
AD转换的Matlab程序,将输入电压转换成时间(脉冲宽度信号)或频率(脉冲频率),然后由定时器/计数器获得数字值(AD conversion of the Matlab program, the input voltage is converted into a time (pulse width signal) or a frequency (pulse frequency), and then to obtain a digital value by the timer/counter)
- 2012-12-18 11:01:40下载
- 积分:1