verlog通过FPGA实现数字钟

基于FPGA的TLC2543控制器,采用状态进行控制ADC进行转换(The TLC2543 controller based on FPGA, using state control of ADC conversion)

这是一个LCD1602底层驱动代码，TI公司LM3S系列的(This is a LCD1602 underlying driver code, TI company LM3S series)

UML2 apprendre a modeliser a l aide de UML

基于DDS的信号发生器设计。DDS,FPGA,Verilog。(Design of signal generator based on DDS.DDS,FPGA,Verilog.)

说明：  设计11位巴克码序列峰值检测器，巴克码相关器原理：巴克码相关器能够检测巴克码序列峰值，并且能够在1bits错误情况下检测巴克码序列峰值。(A 11-bit Barker code sequence peak detector is designed. The principle of Barker code correlator is that the Barker code correlator can detect the peak value of Barker code sequence and detect the peak value of Barker code sequence in the case of 1 bits error.)

自适应滤波器是指利用前一时刻的结果，自动调节当前时刻的滤波器参数，以适应信号和噪声未知或随机变化的特性，得到有效的输出,本设计在MATLAB仿真的基础上，使用verilog实现，附带仿真波形图，实用性强

Used for Time shifting discrete signals, it can do both integral and fractional sampling period delay. Original.

fifo是大多数设计中非常重要的模块；

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使用nios2点亮一个led灯，使用软件quartus13.0，开发板de2-115(nios2 led quartus13.0 de2-115)