一个多路复用器的一个点，用VHDL语言写的。

加法器，输入两个整数，用电路图形式将其逻辑原理呈现出来，该加法器为8位运算，每一位都对应一张电路图，可展示其完整过程(Adder, input two integer, with circuit diagram form its logical principle appear, this adder is 8 bit arithmetic, each corresponding to a circuit diagram, can show the complete process)

USB 1.1 PHY的代码，verilog语言 USB 1.1 PHY的代码，verilog语言-USB 1.1 PHY code, verilog language USB 1.1 PHY code, verilog language

this is code verilog

AES 128 bit with various device interface on FPGA

LDPC码的短循环对LDPC码性能的影响 (Short Protograph-Based LDPC Codes)

大屏幕led点阵显示的驱动时序。 使用vhdl语言描述。其中rom文件可以使用lpm_megcore自动生成。-big screen led to the dot matrix display driver timing. The use of VHDL description language. Rom which documents can be automatically generated using lpm_megcore.

用max+plusII编写的vhdl程序 乒乓球游戏机-with max plusII vhdl procedures for the preparation of the table tennis game

该源代码是RS（31，19）码的完整编译码程序，采用的是VerilogHDL语言，包含了RS码的编码和译码，这蛋疼的东西花费好多时间(The source code is RS (31,19) code complete encoding and decoding procedures, and spend a lot of time using is VerilogHDL language contains the encoding and decoding of RS codes, this egg pain)

VHDL cyclic redundancy check generator und receiver

华莱士树乘法器，运用了华莱士树状结构和布斯算法，提高了速度(The Wallace tree multiplier uses the Wallace tree structure and the Buss algorithm to increase speed)