数字频率计数字频率计

在汉明码调试中实现了纠错原理，达到更快的效果，更少的资源浪费

fpga实验板上16*16点阵显示汉字的程序-翻译结果fpga实验板上16*16点阵显示汉字的程序(Experimental fpga board 16* 16 dot matrix display Chinese program- translation results fpga experimental board 16* 16 dot matrix display Chinese characters in the program)

Inroduce the LEON 2 microprocessor

该程序是一个可完成订制化的SPI双向总线接口，时钟相位、极性，以及分频比全部可通过寄存器进行配置，已经在ISE下通过综合，占用资源少，强烈推荐 (The program is a complete custom of SPI bidirectional bus interface, clock phase, polarity, and the divider ratio can all be configured through the register, has been in the ISE through an integrated, small footprint, it is strongly recommended)

基于vhdl的PWM发生器-VHDL-based PWM generator

powerlink最新的开源全部VHDL及C/C++代码，用于powerlink的开发。是当前最新版本。包含Linux的实现及nios /arm软核的实现。可以用于xinx和Altera的FPGA。

节约资源型 8位*8位 运算VHDL代码，采用串行运算，8 个时钟周期完成一次运算。QUARTUS下已验证(resource conservation-8* 8 Operational VHDL code, using serial computation. 8 clock cycles to complete an operation. QUARTUS has been under test)

设计制作一个检测4*4矩阵键盘的按键编码的实验，把实际按键的键值的八位编码先转换成从0000—1111的编码，再译成数码管能识别的八位编码，在数码管动态显示时，4*4矩阵键盘的第一行对应00—03，第二行对应04—07，第三行08—11，第四行对应12—15。(Design a 4* 4 matrix keyboard key coding experiments to detect the key the actual key octet coded first convert from 0000-1111 encoding, and then translated into digital tube to identify the eight coding, digital tube dynamic display, the first line of the 4* 4 matrix keyboard corresponding to 00-03, the second line corresponds to 04-07, the third line of 08-11, the fourth line corresponds to 12-15.)

实现dsp与fpga的emif的verilog异步实现，可实现异步读写以及相应功能模块控制，文件中包含仿真后的波形图形以及仿真测试程序，运行环境quartus ii11.0，仿真环境mmodelsim se 6.5d(Achieve dsp and fpga verilog asynchronous implementation of the emif, enabling asynchronous reading and writing as well as the corresponding function module control, the document contains graphics, and after the simulation waveform simulation testing procedures, operating environment quartus ii11.0, simulation environment mmodelsim se 6.5d)

各种常用模块的VHDL描叙实例，PDF格式-various modules used VHDL depicts examples, PDF format