数字频率计数字频率计

基于nios ii 控制altera de1 开发板上iic总线实现与at24c02通信-Based on nios ii controlled altera de1 Development Board iic bus for communication with the at24c02

说明：  基于FPGA的串口发送和接收，使用的verlilog语言(Using Verilog serial port program, send and receive.)

at070tn83 800x480 tft lcd verilog 測試 quartus 文件 (800x480 tft lcd at070tn83 testing project file)

VHDL语言实现摄像头的捕捉和采集,通过仿真验证，很好哈-vidicon s catch and collection in VHDL

利用VHDL实现CPLD（EPM240T100C5）的VGA屏幕输出-Using VHDL realize CPLD (EPM240T100C5) output of the VGA screen

一个简单的键盘接口模块程序，对键盘输入的数据和时钟信号进行过滤。过滤后的数据信号PS2Df将被送入两个11位移位寄存器中(A simple keyboard interface module program filters keyboard input data and clock signals. The filtered data signal PS2Df will be fed into two 11-bit displacement registers.)

基于FPGA的uart控制器，波特率可选，VHDL编程，Quartusii 6.0 平台，vhdl语言编程-FPGA-based UART controller, an optional baud rate, VHDL programming, Quartusii 6.0 platform, vhdl language programming

VHDL描述的跑马灯程序，用于初学者练习-Marquee procedures described in VHDL, for beginners to practice

Vending Machine simulation using Moore sequence

基于DDS的信号发生器设计。DDS,FPGA,Verilog。(Design of signal generator based on DDS.DDS,FPGA,Verilog.)