《Verilog HDL 程序设计教程》7

this file describes the steps in building a fifo buffer module in verilog hdl and programming them on an fpga device

该程序实现的是n位全加器，首先用与非门实现一位全家器，最后实现n位的全加器。-the program is to achieve the n-bit full adder, first using the door with non-realization of a family- and finally realize the full n-bit adder.

多功能数字钟，1、采用24小时制：时、分、秒计时、显示。 2、具有手动校准功能：分为时校准、分校准。 3、秒复位 4、闹钟功能 5、整点报时：仿中央人民广播电台整点报时信号

基于Verilog HDL的完整数字跑表工程，在试验机台上运行验证通过了的。 用8位7段数码管分别显示微妙，秒，分。 有开始，暂停，复位功能。 学习VerilogHDL的经典例子，添加了显示功能。-Complete Verilog HDL-based digital stopwatch works in the test machine is running verify pass the platform. With 8-bit 7-segment digital tube showed the delicate, seconds, minutes. Has started, pause, reset. Learning VerilogHDL classic example of adding a display.

OpenRISC 1200 cpu with integrated patches to support ORPSOC and FuseSOC builders

verilog ADPLL file with testbench.v

本设计是基于FPGA设计一个地铁自动售票系统。 本设计采用自顶向下的模块化设计方法，基于FPGA使用VHDL语言设计制作一个地铁自动售票控制系统，该系统能出售2条线路3种不同价位的票，完成售票、找零、显示等功能。(The design is based FPGA design of a subway ticket vending system. This design uses a top-down, modular design method, a subway ticket vending control system based on FPGA using VHDL language design, the system can sell two lines of different priced tickets, complete the ticket, give change, display and other functions .)

detailed spec for Xilinx V5 FPGA, reference for programming of FPGA, system designer or ASIC designer.

实现数字变下频的matlab程序，CIC,HB,FIR滤波器代码都在其中(Realize digital variable frequency under matlab, CIC, HB, FIR filter code in it )

BulkIn是FPGA向CY7C68013发送数据 BulkOut是FPGA从CY7C68013接收数据,可以用LED显示 -BulkIn is the FPGA to the CY7C68013 is BulkOut send data CY7C68013 receive data from the FPGA, you can use LED display