《Verilog HDL 程序设计教程》7

高级FPGA设计__结构、实现和优化,中文翻译版(Advanced FPGA Design- Architecture, Implementation, and Optimization)

基于DS1302芯片的VERILOG 语言数字钟。可实现年月日时分秒显示。(DS1302 chip-based language VERILOG digital clock. Date can be achieved when every minute display.)

说明：  BUS documentation and map reffereces

C6000系列之6701开发板相关文件及说明(C6000 Series of 6701 development board-related documents and notes)

10G高速以太网mac VERILOG源码 可仿真可实现(10G high speed Ethernet MAC verilog code can be used for synthesis or inplementation)

具有16个校验位的RS编码器，在FPGA上实现。(With 16 RS encoder, the parity bit in the FPGA.)

从FPGA输出到HDMI Tx的verilog 模块。实现完整HDMI图像输出功能。(FPGA output to HDMI Tx module in verilog)

verilog实现UART收发功能，硬件平台为spartan 6，软件平台为ise14.7(verilog implement UART rx and tx function)

4x4键盘模块。这个文件包括普通的键盘设计方案说明和相关的原程序。-4x4 keyboard module. The documents include ordinary keyboard design program descriptions and procedures related to the original.

In this design, it is assumed that a buffer sized as 1024x8 bits provides main data including scale factors and Huffman code bits to Huffman decoder. Also, it is assumed that a memory with 1024x8 bits is ready for each component to write or read the output or input 576 frequency lines.(This folder contains three directories: Huffman, IMDCT and Filterbank, each of them includes all the VHDL source codes of the component.)