《Verilog HDL 程序设计教程》7

simple code based on verilog shifter , cla ,clg

PCIe demo sample code

evga-indtube.h - Keytable for evga_indtube Remote Controller.

4通道12位AD芯片 AD7862控制模块,VHDL源代码,适于单次转换采样,250K采样率.-4-channel 12-bit AD chip AD7862 control module, VHDL source code, suitable for single conversion sampling, 250K sampling rate.

这个是讲pll的具体用法的,一般在fpga设计中都会用到 他,这个是lattice的xp2的pll的介绍,不过,fpga 都是相通的其他两家也差不多(Pll say this is the specific usage, the general design in the FPGA will use him, this is the lattice of the pll of xp2 introduction, however, fpga are connected to other two similar)

hi this is an verilog codes

基于MAX2运用Quartus实现串口通信-MAX2-based use of Quartus Serial Communication

键盘输入串口输出显示字符,通过串口显示键盘输入的字符-Keyboard input serial output display characters, the keyboard input through serial display characters

华为内部的FPGA设计培训教程，详细阐述了设计流程图、Verilog HDL设计、逻辑仿真、逻辑综合。对大家的学习一定有帮助的。-Huawei within the FPGA design training tutorial, a detailed flow chart of the design, Verilog HDL design, logic simulation, logic synthesis. Study of the U.S. must have help.

Xilinx FPGA make 50 smaller-Xilinx FPGA make 50 smaller