VHDL出租车计费代码

fpga里实现 uart 经典 vhdl语言写的 ise工程文件-fpga implementation in vhdl language classic uart of ise project file

1路视频光端机的接收端，VHDL源码，使用全FPGA芯片的硬件，内建解帧、时钟、DESERDES-PDH a video of the receiving end, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES

Used for Time shifting discrete signals, it can do both integral and fractional sampling period delay. Original.

verilog HDL语言，对于超大规模集成电路开发学习非常有好处-verilog HDL language, for ultra-large-scale integrated circuits are very beneficial to the development of learning

SAP-1硬件描述语言（使用Verilog语言）

数字时钟，可以实现(1) 显示日期功能（年、月、日、时、分、秒以及） (2) 可通过按键切换年、月、日及时、分、秒的显示状态 (3) 可随时调校年、月、日或时、分、秒 (4) 可每次增减一进行时间调节 (5) 可动态完整显示年份，实现真正的万年历显示 (6) 可显示温度 (Digital clock, can be achieved (1) the date function (year, month, day, hour, minute, seconds as well) (2) through the key switch the year, month, day in a timely manner, minute, second display state (3) at any time adjust the year, month, day or time, minutes, seconds (4) can be added or deleted, a time adjustment (5) can be dynamically complete display Year, the real calendar display (6) to display temperature)

串行数据开发实用代码， 适合初级学习者使用 很不错(Serial data to develop a practical code for primary learners use very good)

DDS信号发生器，能产生多种波形，正玄波，三角波，方波，频率可调，相位可调-DDS signal generator, can produce a variety of waveforms, are mysterious wave, triangle wave, square wave, frequency tunable, phase adjustable

里面包含了三段代码，主要是用matlab产生高斯随机信号以及高斯白噪声和色噪声，然后计算其数字特征及对这些信号进行频谱分析和功率谱分析，里面还有关于低通滤波器的设计的简单说明(Which contains three sections of code using matlab Gaussian random signals and white Gaussian noise and color noise, and then to calculate the numerical characteristics and spectral analysis and power spectral analysis of these signals, there is also the low-pass filter design BRIEF DESCRIPTION OF)

wishbone 源代码，opencore-wishbone source code, opencore