VHDL出租车计费代码

用Verilog语言编写的对m序列进行汉明码编译码的程序。具体实现为产生m序列后对其进行(7,4)汉明码编码并加错，然后将其纠错译码并输出，详细过程见仿真。(Written by Verilog m sequence of procedures for coding and decoding Hamming codes. Concrete realization of m sequence to produce its (7,4) hamming code and a mistake, and then error correction decoding and output, see the detailed process simulation.)

Cadence的VHDL运算库包，实现求方根，平方你是不是以前不知道怎么弄．哈哈．-Cadence VHDL Operational the package, seeking to achieve root, You are not square did not know how get. Ha ha.

AES算法部分模块行位移列变换以及主题程序加密解密(AES algorithm transforms part of the module rows and columns relating to the displacement of encryption and decryption program)

This is counter with T_FF.

Program for simulate a prtsc

说明：  Verilog code for implementing simple ALU.

基于FPGA的JPEG解码，对开发图片解码的人有用。(FPGA-based JPEG decoding, the development of image decoding useful.)

Implementarea unui comparator pe 1 bit

使用FPGA透过RS232与PC的作沟通，

一个八位的并行输入，串行输出的编码器；带有开头结尾帧。(It is an encode with eight palallel input and a serial output.)