altera EP1C6Q240C6开发板原理图

de2开发板上的一个小程序 模60的计数器/分频器(de2 board developed a small program module 60 of the counter/divider)

广东工业大学硕士论文《SVPWM算法优化及其FPGA/CPLD实现》，在详细分析经典SVPWM算法基础上，提出一种优化算法，并在FPGA上实现。论文附录包含VHDL源码。(Guangdong University Thesis " SVPWM algorithm to optimize its FPGA/CPLD realization" in the detailed analysis of the classical SVPWM algorithm is proposed based on an optimization algorithm, and implemented on FPGA. Paper appendix contains VHDL source code.)

编写 VHDL 代码为 4 x 1 多路复用器，使用下面的方法 (1) if else 语句 (2) case 语句 (3) 与声明

纠错和单故障检测代码使用正交拉丁方是用VHDL语言写的。

《Verilog HDL 程序设计教程》5-"Verilog HDL Design Guide" 5

Convert Roman numerals to integers

当年本科时的毕业设计，信号发生器和频率计-The time of the year undergraduate graduate design, signal generator and frequency counter

自己编写的经过QuartusII验证的Verilog HDL程序，可以实现常见功能-After QuartusII their written procedures for verification of the Verilog HDL, can achieve common features

FPGA 控制MPU6050陀螺仪传感器，通过串口把数据打印出来(FPGA controls the MPU6050 gyroscope sensor and prints out the data through the serial port)

说明：  VHDL BISS,SSI,ENDAT2.2, ENCODER