In Altera

4选1数据选择器，有使能端控制，4个数据输入，2个地址端，1个输出(4 1 data selector, enable end control, four data inputs, two addresses end, an output)

设计含异步清零和同步时钟使能的加法计数器-Clear design with asynchronous and synchronous clock so that the adder counter

这是一个瑞萨R78/G13的SPI演示程序，详细的放置了说明，很有用的源码(This is one of the SPI Renesas R78/G13 demonstration program, placed a detailed description of very useful source)

说明：  altera发布的开源8b10b源代码，vhdl语言描述(altera released the source code open source 8b10b, vhdl language description)

在Quartus环境下编写，使用Cyclong系列芯片，配置七通道高精度AD5791，该例子为AD5791的FPGA配置使能代码,包括模拟数据输入模块，复位模块，命令接收是能配置模块。(AD5781，Digital signal convert to Analog signal)

用Verilog语言实现了UART串行通信协议(Verilog language used to achieve a UART serial communication protocol)

说明：  DA芯片输出控制 SPI协议 只写不读 FPGA用 verilog(DA-chip SPI protocol output control does not read write-only FPGA with verilog)

基于verilog的1588V2协议的fpga实现，目前项目通用代码，供大家参考(Based on verilog 1588 v2 fpga implementation of the agreement, the project general code, for your reference)

(Springer Series in Advanced Microelectronics 51) Ayan Palchaudhuri, Rajat Subhra Chakraborty (auth.)-High Performance Integer Arithmetic Circuit Design on FPGA_ Architecture, Implementation and Desig

vhdl,序列信号检测模块，此模块检测1110010，可改为任意序列，输出电位为1为检测出，否则为0-vhdl, sequence of signal detection module, this module testing 1.11001 million, can be changed to an arbitrary sequence, the output potential of an as detected, otherwise 0