In Altera

开发系统上采用的时钟信号的频率是20MHz，可分别设计计数器对其计数，包括计秒、分、小时、日、周、月以及年等。在每一级上显示输出，这样就构成了一个电子日历和时钟的模型。为了可以随意调整计数值，还应包含设定计数初值的电路-Development system using the clock signal frequency is 20MHz, the design can be counter to its count, including seconds, minutes, hours, days, weeks, months and years. At every level to show the output, thus constitutes an electronic calendar and clock models. Can also adjust the order value, should also be included in setting the initial count circuit

Altera的CycloneIII Start Board,使用的PFGA是3C25，包括原理图和PCB，用Cadence Allegro打开-Altera

DDS调试心得,VERIOLG 各HDL和VHDL语言的DDS调试方法-DDS debugging experience, VERIOLG the HDL and VHDL languages DDS debugging method

fpga控制led灯的闪烁，内容简单，希望对初学者有用.(fpga control led lights flashing, the content is simple, I hope useful. . .)

基于CS的一维距离像（HRRP）及FFT成像对比(CS-based HRRP and FFT HRRP)

ADC-DAC transmittion works thru SPI on 25 MHZ. Used for some student project on Xilinx sprtan3a FPGA

本设计主要用来进行图像采集处理，通过摄像头采集图像信息，经过插值算法后存储到外部SDRAM，然后读取图像数据，进行边缘滤波处理后经VGA输出到屏幕上。(This design is mainly used for image acquisition and processing,through the camera capture image information,after interpolation to the external memory after the SDRAM,and then read the image data processed by the edge filter VGA output to the screen.)

说明：  点亮led流水灯，通过调用锁相环，可以更改对应的时钟。(Lighting the LED pipelining lamp, the corresponding clock can be changed by calling the phase-locked loop.)

5对于进入密码锁的钥匙，假设复位后七节灯显示为" 0"，而使用sw1、sw2两个，则sw2-> sw1-> sw1-> sw2，则表示解锁右侧将导致七节灯显示为" 8"

VHDL产生时钟50分频程序，供初学者参考-VHDL generated clock frequency of 50 procedures, the reference for beginners