In Altera

它是一个基于verilog的数字时钟，显示时-分-秒，它可以手动输入，并为时、分和秒分配3个开关第二，它数字时钟频率是实时设置的。我自己用逻辑开发的。。。

The objective of this project is to design and implement the controller for an electronic safe. You will interface a 16-button keypad to the NIOS boards. The combination code of the safe will be the last

基于FPGA的视觉电生理图像刺激系统的设计(Based on the design of FPGA visual electrophysiology image stimulation system)

FPGA做VGA视频显示的详细资料，我找了很久才收集起的，有四篇文章，很有用(FPGA do VGA video display detailed information, I found a long time before they start collecting, with four articles, very useful)

说明：  载波同步是QPSK信号相干解调的一项关键技术。(Carrier synchronization signal coherent QPSK demodulation is a key technology.)

8aqm调制串并转（1:3）换部分vhdl程序(8aqm string and convert vhdl program)

用Verilog实现一个基于Mesh拓扑结构的路由器网络(Using Verilog to implement a router network based on Mesh topology)

VHDL数字系统设计和工程实践6，包含原理，真值表和原理图，以及VHDL源代码.-VHDL digital system design and engineering practice, six, including the principles, truth table and schematic, as well as VHDL source code.

4通道12位AD芯片 AD7862控制模块,VHDL源代码,适于单次转换采样,250K采样率.-4-channel 12-bit AD chip AD7862 control module, VHDL source code, suitable for single conversion sampling, 250K sampling rate.

一个简单的微处理器的实现，能够进行几种常见的操作，对于熟悉计算机的工作原理很有帮助，并且附有详细的设计报告和设计思路。在word文档最后给出了源代码。-a simple microprocessor to achieve, for several common to the operation of the computer for those familiar with the working principle helpful, and with the detailed design reports and design ideas. The word is the final document source code.