基于FPGA的uart控制器，波特率可选，VHDL编程，Quartusii 6.0 平台，vhdl语言编程...

该程序实现的是n位全加器，首先用与非门实现一位全家器，最后实现n位的全加器。-the program is to achieve the n-bit full adder, first using the door with non-realization of a family- and finally realize the full n-bit adder.

基于xilinx公司的SPARTAN6系列芯片的高速全双工串行收发器(high-speed transceiver based on spartan 6 of Xilinx PFGA)

16b20b encoder and decoder

使用VHDL编程的异步FIFO程序 经调试可运行-Using VHDL programming asynchronous FIFO procedure can be run by the debugger

关于语音通信信道调制的程序代码，是论文的仿真程序(About voice communication channel modulation code, the authors of the paper simulation program)

通过UART进行的低功耗低成本的数据传输TEQ再检查一下它，一旦它的writen用Verilog语言而且它是基于一个协议，你要指定更好的沟通自己的规则

液晶ST7565P_12864驱动，实现打点成图。(LCD ST7565P_12864 drive, dot mapping.)

SPI Verilog code with programmable clock

主要编写了一组二进制数据通过根升余弦滤波器后的波形，但并没有使用ISE内部的FIR滤波器内核，该程序相当于编写了一个根升余弦滤波器。(Mainly prepared a set of binary data through the root raised cosine filter waveform after, but did not use the ISE internal FIR filter kernel, the program is equivalent to the preparation of a root raised cosine filter.)

波形产生器：用VHDL编写的波形产生器程序-Waveform Generator: Using VHDL prepared waveform generator procedure