iic程序

标准RS422 Verilog源代码， 传输波特率可以修改， FPGA上可以工作(Standard RS422 verilog communication source code, buardrate can be updated and it is fully work in FPGA )

资源描述 modelsim输出文件代码演示 verilog  内含头文件和testbench.Verilog HDL是一种硬件描述语言（HDL:Hardware Description Language），以文本形式来描述数字系统硬件的结构和行为的语言，用它可以表示逻辑电路图、逻辑表达式。  

Northwest Logic公司（Altera公司）SDR SDRAM控制器的Verilog，由微米SDR SDRAM测试。

这是个双端口双端口ram的定义，当然读者在此基础上还可以扩充(This is a dual-port dual-port ram definition, of course, on the basis of the readers can also be expanded)

This CAN Controller was tested with the Bosch VHDL Reference Model and passed all the tests. Because of the licensing issue it can not be published on the Opencores web site. The Can Controller was also implemented in real HW (12 boards were constantly talking to each other). The included test bench is not a real test bench and should be improved. However a volunteer is needed for such a job. I can provide some help but am not willing to write it by myself.

800 x 480 / inch lcd

滤波器的实现，总共为4种，是简单的coif3滤波器的实现方法(The implementation of the filter, a total of 4, is a simple coif3 filter implementation method)

基于FPGA的三相异步电机变频调速程序,对三相桥式逆变器进行控制，采用VVVF调速方法，红外遥控设置频率。 基于FPGA的三相异步电机变频调速程序,对三相桥式逆变器进行控制，采用VVVF调速方法，红外遥控设置频率。 基于FPGA的三相异步电机变频调速程序,对三相桥式逆变器进行控制，采用VVVF调速方法，红外遥控设置频率。

FPGA驱动VGA在电脑显示屏上显示彩条                                                                                                                        附有注释

FPU (Floating Point Unit) is very useful in the moden ASIC and SOC designs. This module has been verified by FPGA and EDA env. But if you want to use it in a real project, please verify it with some formal method.