AHB 转移到 APB 源和建业读/写 verilog 代码

说明：  用uvm验证方法学验证异步fifo，文件包括异步FIFOrtl代码和uvm组件(Verification of asynchronous FIFO with UVM)

This is the update firmware for CVFX-C02, 7" motorized touch screen car dvd player gps

阿尔法贝塔滤波器，是卡曼滤波器的简化，比卡曼滤波器速度快。这是一个实例。(aplha-beta filter is filter that faster than kalman filter)

说明：  配置GTH ip的例子工程，选用7 series 芯片的GTH 113quad的四个通道，在程序中每个链路利用自己的恢复时钟进行数据解码，所以四个通道可以各自独立运行；成功工作在2.54Gb/s的链路状态，长时间（>24小时）的测试，误码率一直为0.(The GTH ip example project is configured with four channels of the GTH 113quad of the 7 series chip. Each link in the program uses its own recovery clock for data decoding, so the four channels can operate independently; the successful operation is at 2.54Gb/ The link state of s, long time (>24 hours) test, the bit error rate has been 0.)

高速串行设计FPGA-GTX IP设置生成drp模块，可动态配置速率2.4Gbps，1.2Gbps，0.6Gbps，自适应链接(High-speed serial design FPGA-GTX IP setting generation drp module, dynamically configurable rate 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link)

本程序可以在DE1-SOC的实现10进制的FPGA数字计数器

Verilog数字系统设计教程(第二版) 夏宇闻(Verilog Digital System Design Course (2nd Edition) Xia Yuwen)

，笔者准备采用LCD1602字符液晶作为载体，来实现“Hello World”的显示。雷同于前面MCU按键消抖动方案1的C语言代码移植一样，此处我们准备以状态机的方式，移植LCD1602的驱动代码到Verilog HDL中，驱动实现LCD

VHDL数字电路设计教程 乔庐峰等译 当当网销量领先(VHDL tutorial on digital circuit design: (Brazil) Pedroni (Pedroni, VA) were, Joe Lu Feng, M. Publisher: Electronic Industry Press Dangdang sales leader)

一些verilo的经典实例，非常适合初学者(verilo of the classic examples, for beginners)