数字频率计(试验报告)适合初学者参考

fir滤波器，Verilog语言写的，容易看懂-fir filter, Verilog language written in easy to understand

一个以太网卡的硬件描述，可以参考进行设计网卡芯片。-an Ethernet card hardware description, reference card chip design.

设计一个8位有符号数字平方器。平方器将接收操作数B，一个8位有符号数。新兴市场；

说明：  该文件包含了实现单周期cpu的全部代码以及实验报告，包括仿真波形以及烧板过程(This file contains all the codes and experimental reports of realizing single cycle CPU, including simulation waveform and download process)

基于fpga和xinlinx ise 的7段码led显示程序，希望对你有所帮助-and ideally xinlinx 7 of the code led display program, and I hope to help you

xilinx spartan6的pcie pio源代码(xilinx spartan6 pcie pio demo)

VHDL与源代码包-and VHDL source code

quartus II-sopc builder avalon总线LCD控制IPCORE-quartus II-sopc builder avalon Bus LCD controller IP CORE

32位二进制除法器2

说明：  DDS的基本原理主要由五部分组成，分别是；相位累加器，正弦波形存储器，数模转换器，低通滤波器和时钟，将相位累加器输出的数据作为地址，用来查询表的数据，将取出的正弦数据通过数模转换器输出模拟信号，模拟信号再通过一个低通滤波器输出纯净的正弦波信号。(The basic principle of DDS is mainly composed of five parts: phase accumulator, sinusoidal waveform memory, digital to analog converter, low-pass filter and clock. The output data of phase accumulator is used as address to query the data of table. The extracted sinusoidal data is output analog signal through digital analog converter, and the analog signal is output pure sine through a low-pass filter Wave signal.)