七人抢答器 可做课程设计 能仿真 一人抢完其他人锁定

i2c core : i2c master top

此程序为串行通信程序,采用verilog语言编写的,经过仿真验证已经通过.-This procedure for the serial communication procedures, the use of Verilog language, after simulation has been adopted.

利用VHDL语言实现PID控制,已经过调试验证。(Using VHDL language to implement PID control)

说明：  掌握SDRAM数据读写、刷新、初始化以及FPGA串口收发时序，熟练FIFO IP核的生成和调用。(Master SDRAM data read and write, refresh, initialization and the timing of sending and receiving of the serial port of the FPGA, skilled in the generation and invocation of the FIFO IP core.)

实验用16位全加器的VHDL代码，适合初学者学习，数电学习的好工具。 (Experiment with 16-bit full adder VHDL code for beginners to learn, a good tool to learn a few power.)

UG二次开发，课程作业，研究生，学习，初学者，打孔，复杂体，阵列 UG C program，homework，student，study，first，hole，complex，many( UG C program，homework，student，study，first，hole，complex，many)

verilog da0832 cpldfpga control-verilog da0832 cpldfpga control

用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证(verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider )

the 8 bit alu by verilog

用状态机对A/D转换器0809的采样控制电路的实现。工具：Quartus ii 6.0 语言：VHDL-State machine used for A/D converter sampling control circuit 0809 is achieved. Tools: Quartus ii 6.0 Language: VHDL