pn sequence generator

OpenRISC 1200 cpu with integrated patches to support ORPSOC and FuseSOC builders

参数可配置的sequential 乘法器和booth 乘法器(verilog source code with configurable parameters for sequential multiplier and booth multiplier )

基于有限状态机的健壮性测试研究。 关键词：健壮性测试；增强有限状态机；全球平台；安全通道协议(The Research of Robustness Testing Based on FSM)

modelsim设计的可调占空比的方波程式-modelsim designed adjustable duty cycle of the square wave program

本程序用于实现OFDM信道估计的LS算法的硬件仿真，基于FPGA开发的VHDL编写，给出了各模块的仿真波形图，供大家交流参考。

Nonlinear discrete system identification, It uses a pulse of consumer law, Partial least squares method.

TASKS OF TWO TYPES CAN BE RUN FOR EVERY 2 MIN.

三种方法编写多路选择器的VHDL源代码 分别使用if else ,select ,when 语句-three methods to prepare multiple choice of VHDL source code were used if else, select, when words

数字钟的VHDL源程序，可以实现校时，校分等功能，并在试验箱上运行成功-The VHDL source code digital clock, you can achieve at school, school grade features, and success in the chamber is running on

说明：  本工程使用A7系列FPGA产生DDS，用DAC0832进行正弦电压输出(In this project, A7 series FPGA is used to generate DDS, and DAC0832 is used for sinusoidal voltage output)