pn sequence generator

自己编的VGA彩条信号发生器verilog ise环境-Own the VGA color signal generator verilog ise Environment

parity encoder test bench

VHDL_ 两个电路计数上 / 下液晶显示语言 VHDL (海 mạch đếm lên/xuống hiển 施耐液晶 bằng ngôn ngữ VHDL)

本文介绍了使用verilog语言进行硬件设计的一些基本技巧-This paper describes the use of Verilog hardware design language, the basic skills

matlab dsp building 工程欢迎下载(matlab dsp building )

designing of 16 bit adder using 4 bit adder using verilog code

这份文献主要介绍了dsp builder 8.0的功能及使用手册，介绍了如何和matlab一起使用的步骤。(This literature focuses on the dsp builder 8.0 features and user manual describes how to matlab and used in conjunction with steps.)

实现基于FPGA的vga显示，亲测能编译得过，不同开发版应该要相应改动（PS: 不太了解）

DE2-70,NIOS reference file,

VHDL USB2.0接口源码,内有说明,详细.-VHDL USB2.0 interface source code, which is described in detail.