file_read vhdl code provide by my teacher for reading file into FSM

Alter kit FPGA de2-35 This project shows a cascade motion through board leds.-Alter kit FPGA de2-35 This project shows a cascade motion through board leds.

以嵌入式CPU和FPGA为基础的嵌入式系统架构-Embedded CPU and FPGA-based embedded system architecture

图像采集、存储控制verilog源代码，fpga控制SAA1117,采集数据存储到sram，仿真编译测试都能通过(Image acquisition, storage, control verilog source code, fpga control SAA1117, collecting data to sram, simulation tests can be compiled by)

说明：  CPU设计，包含基本的指令集，能执行简单的程序。考虑了CPU，寄存器，存储器和指令集之间的关系。即读写寄存器，读写存储器和执行指令。(CPU design, including basic instruction set, to execute a simple program. Consider the CPU, registers, memory, and the relationship between instruction sets. That read and write registers, read and write memory and execution.)

基于stm32开发平台的，模拟ad采样程序设计，可直接下载使用(stm32 zhijiexiazaishiyong)

LTE is an abbreviation for Long Term Evolution.

说明：  verilog 编写的ldpc编码，含有两个文件(LDPC written by Verilog)

双向移位寄存器的VHDL源程序,自己做实验编写的可以用 谢谢大家-Bi-directional shift register of the VHDL source code, prepared by their own experiments can be used Thank you

VHDL语言100例详解，北京理工大学ASIC研究生出版，这里是1-20个examples-VHDL language of 100 cases explain, Beijing Institute of Technology, Graduate ASIC published examples here is 1-20 months

This verilog vga test circuit