递增方式在4位数码管上向上计数显示从0000

Verilog 编写的网卡DM9000A的IP核，altera公司寄的DE2系统中的源程序核-Verilog prepared DM9000A the IP core network card, altera company sent DE2 System source of nuclear

全自动洗衣机的控制器。 1.洗衣机的工作步骤为洗衣、漂洗和脱水三个过程，工作时间分别为：洗涤10秒，漂洗5秒，脱水5秒； 2.用一个按键实现洗衣程序的手动选择：A、单洗涤；B、单漂洗；C、单脱水；D、漂洗和脱水；E、洗涤、漂洗和脱水全过程； 3.用显示器件显示洗衣机的工作状态（洗衣、漂洗和脱水），并倒计时显示每个状态的工作时间，全部过程结束后，应提示使用者； 4.用一个按键实现暂停洗衣和继续洗衣的控制，暂停后继续洗衣应回到暂停之前保留的状态； (Automatic washing machine controller. 1 washing machine work steps for the laundry, rinsing and dehydration three processes, working hours are as follows: washed for 10 seconds, rinse for 5 seconds, dehydrated five seconds 2 with a button to manually select the program to achieve laundry: A, single-washing B, single rinse C, a single dehydration D, rinsing and dehydration E, washing, rinsing and dehydration the whole process 3 with a display device display the working status of washing machine (laundry, rinsing and dehydration), and each state countdown show working hours, after the whole process should prompt the user 4 laundry with a button to pause and continue control of laundry, laundry should be back after a pause pause before continuing to retain the state )

LFSR模块，单个模块，实现移位寄存器，生成测试用pattern-LFSR

vhdl code for cyclic cfft control

FPGA开发超声波测距，可改写工业探伤或倒车测距等系统，quartus2下选择EP2C5Q208C8（CycloneⅡ） 支持目前淘宝上能买到的所有4-5针超声波模块 应用cycloneⅡ自带除法模块 开发板为有光技术YG2.1 生成电路规模较小 ！！注意：移植程序仅需重新约束数码管和超声波模块的针脚 (Ultrasonic Ranging FPGA development, industrial inspection or reverse rewritable ranging systems, EP2C5Q208C8 (CycloneⅡ) under quartus2 4-5 needle ultrasonic module supports all currently scouring the treasure can buy Applications cycloneⅡ own division module Development board bright technical YG2.1 Small scale generating circuit ! ! Note: The migration program only re-constraint digital and ultrasonic modules Pin)

实现I2C协议下EEPROM存储的数据读写控制(Under I2C protocol to achieve read and write data stored in EEPROM control)

PCIe数据链路层的协议详解，对做PCIe接口有非常重要的指导价值。(PCIe data link layer protocol detailed, do PCIe interface very important value.)

利用Verilog HDL对AD7705进行控制ADC采样，实验室师兄的-Using Verilog HDL to the AD7705 control ADC sampling, laboratory师兄the

说明：  用VHDL语言实现电子钟(Using VHDL language electronic bell)

潘松编写的EDA书籍！学习FPGA的好帮手！-Pinson prepared by the EDA books! Learning FPGA a good helper!