占空比1：1的通用分频模块

此代码是由FPGA产生SPWM波的代码，简单易懂(use FPGA to generate SPWM)

此代码是用于旋转一个步进电机所需的方向。

FPGA控制AD逐点采集信号，并将AD转换后的数据串行发送出去。-FPGA to control the signal sampling point by point AD, AD conversion and serial data sent.

实用的程序代码，希望对大家有用，已经调试通过-Practical program code, in the hope that useful to everybody, has debugging through

说明：  BUS documentation and map reffereces

程序在报告中，要　用QuartusII运行，注意从word到运行环境中，可能有个别符号不兼容，重新在运行环境中输入那些符号就可以了-procedures in the report, with QuartusII operations, the attention to word from the operating environment, Some individual symbols are not compatible, the operating environment to re-enter those symbols on the

用VHDL编写的串口通讯程序，包括几个不同的程序例子，也可以用verilog进行改写。()

基于NIOS II 的DE1开发板的VGA 控制器VGA控制模块主要控制VGA模块的开始和其运行的状态，需要写一个Avalon 从端口响应CPU的控制信号，继而控制整个模块的运行，-Based on the DE1 of the NIOS II development board VGA controller to control the VGA module VGA main control module and its operation began, and the need to write a response to Avalon from the CPU ports of the control signal, and then control the operation of the entire module,

采用SG3525实现感应加热电源的频率跟踪。(SG3525 is used to realize frequency tracking of induction heating power supply.)

ASK调制信号的verilog VHL设计，在ise中实现了ASK信号的调制解调。(ASK modulation signal verilog VHL design, in ise to achieve the ASK signal modulation and demodulation.)