步进电机

verilog中调用门级电路的实验程序，实现了门级舰模-call Verilog gate-level circuit of the experimental procedures, to achieve a gate-level ship-mode

verilog code for 8 bit alu

基于FPGA，利用VHDL语言对小车循迹进行设计。(Car tracking)

关于vhdl的一些例子-on some of the examples of VHDL

关键词：清华大学计算机系 计算机组成原理大实验 多周期cpu工程源码，内含中断，串口，以及31个指令的实现，读写内存，控制器，ALU，寄存器，分频等模块，小作业什么的可以直接从里面摘抄，为学弟学妹造福(Keywords: Department of Computer Science Computer Composition Principle experimental multi-cycle the cpu Engineering source for the benefit of mentees)

sdh帧同步，实现sdh帧搜索，预同步，同步，保护等各态的功能(SDH frame synchronization SDH frame search, pre-sync, synchronization, protection, the function of each state)

说明：  ? 熟悉IIC协议总线协议，采用IIC总线对图像采集传感器寄存器进行配置，并转换为RGB565格式。 ? 利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。 ? 利用 SDRAM 接口模块的设计，实现了刷新、读写等操作；为提高SDRAM 的读写带宽，均采用突发连续读写数据方式；并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。 ? 利用双线性插值方法实现对图像640×480到1024×768的放大操作。 ? 完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format. Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface. With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA. The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768. Complete the VGA display interface design.)

最新热血江湖外挂，需要的可以下载，游戏开心热血江湖应用辅助(Yulgang latest plug-in needed to download, games happy))

QP编程创始人所著的介绍QP编程思想的书，中文版。QP是用于嵌入式中状态机编程的开源软件。(QP programming book written by the founder of the introduction of QP programming ideas, and Chinese version. QP is open source software for embedded state machine programming.)

controller for sending serial data at different speeds