基于FPGA的DDS设计

这是维特比译码器 verilog 代码生成器进行测试和 FPGA 验证。

根据ASMD图设计验证冒泡排序算法。给出设计程序及时序仿真结果，含纸质报告。(According to the ASMD diagram design, verify the bubble sorting algorithm. Give the design procedure and the simulation result in time, including paper report.)

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像边缘提取(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image edge extraction)

基于FPGA，利用VHDL语言对小车循迹进行设计。(Car tracking)

说明：  ip core of the transceiver gtx

VHDL语言编写的I2C通信接口,可与单片机等MCU相连,只占用很少的引脚线完成数据的传输(Written in VHDL I2C communication interface, such as MCU and MCU can be connected, only takes a few lines to complete the data transmission pin)

Array muiltiplier verilog code.. 4 bit two inputs with 8 bit outputs

用Verilog HDL编写的PID程序代码，成功调试，运行良好。(The source code of PID in Verilog HDL.Simulation was successful.)

The Date prototype object is itself a Date object (its [[Class]] is "Date") whose value is NaN.

基于DSP28335的产生ADc采样的程序(Program for generating ADC sampling based on DSP28335)