verilog

简单的12位的AD转换实现，模数转换，实现模拟量转化为数字量，并在液晶显示屏上显示出转化结果，我自己下载到板子，运行正常.

说明：  Matlab - to hdl code for square root

控制电话信令 完成忙碌 等待 回铃音振铃等(Signaling complete control over telephone ring so busy waiting ringback tone)

verilog编写的QPSK发射机的ＦＰＧＡ部分，已经过验证，完全达到要求。调制矢量误差４％(QPSK transmitter verilog prepared by the FPGA portion, has been proven, fully meet the requirements. Modulation vector error of 4 )

音频编码（ADPCM位） ；

异步FIFO 输入: 16bit 输出:16bit 深度:256(Asynchronous FIFO Input: 16bit Output: 16bit Depth: 256)

shift example for verilog

LED灯、跑马灯的显示源程序，包括对代码的说明(Display source code LED lights, marquees, including the code specification)

说明：  formality2016 userguide