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clock_6
ds1302时钟驱动程序,已在quartus上验证可以是直接使用(DS1302 clock driver, which has been verified on quartus, can be used directly)
- 2020-06-24 12:00:02下载
- 积分:1
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mmuart
简单uart,verilog语言编写,已经经过测试,有需要的可以看看(Simple uart, Verilog language, has been tested, you can see if you need it)
- 2020-06-23 20:00:01下载
- 积分:1
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Signed-Arithmetic-in-Verilog-2001
有符号数的完整讲义和例子Verilog 2001(Signed Arithmetic in Verilog 2001, paper with examples)
- 2011-01-18 17:15:09下载
- 积分:1
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test-ram
design ram v8051 for project
- 2013-07-08 23:24:20下载
- 积分:1
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cpu mips
实现多周期mips
设计一个32位MIPS多周期微处理器 具有多种 算数指令:
(Design a 32-bit MIPS microprocessor multi-cycle arithmetic instructions
- 2023-03-29 18:05:04下载
- 积分:1
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AD9957
ad9957的资料,内含有命令字生成器,适合使用该芯片的开发人员(ad9957 data, contains the command word generator for developers using the chip)
- 2011-10-27 22:06:55下载
- 积分:1
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synthesis-bandstop-filters
本例介绍直接合成带阻滤波器的方法,n阶滤波器能实现n个传输零点(A direct synthesis technique of a new class of bandstop
coupled resonator elliptic filters is presented. Two different
coupling schemes, which both include source–load coupling are
used. The first coupling and routing scheme is the standard folded
structure used in implementing bandpass elliptic filters with
transmission zeros using resonators.)
- 2013-03-12 18:19:01下载
- 积分:1
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8位简单的RISC-CPU的设计
精简指令集的整体设计 实现了简单的8位RISC CPU的基础功能,包括加,减,与,或,异或等操作,还可以对RAM进行读取或写入操作。另外,还有RISC_CPU的实验报告,里面包含了RISC-CPU的设计原理及仿真结果。
- 2022-02-21 02:35:37下载
- 积分:1
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xapp1161
多相滤波系统的设计与实现,有MATLAB仿真程序,有sysgen的系统仿真,还有VHDL代码,其中还有FIR的系数参数等等(Polyphase filter system, the design and implementation includes a MATLAB simulation program, sysgen system simulation, and VHDL code, including FIR coefficient parameters, and so on
)
- 2021-02-15 17:29:47下载
- 积分:1
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buffer
用verilog实现的buffer,经过了fpga平台验证。(Implement buffer with verilog.)
- 2020-10-28 12:19:58下载
- 积分:1