modelsim输出文件代码演示 verilog

使用VHDL编写语言，巧妙的利用计数器和循环输出一个坐标系，由于VHDL出现负数比较麻烦，全部由正数代替，输出一个原点在中心，半径128的256×256的坐标。方便坐标变换以及用此坐标做算法。(Use of VHDL language, clever use of counter and loop outputs a coordinate system, because VHDL negative too much trouble, all replaced by a positive number, the output an origin at the center, radius 128 256 256 coordinates. Convenient coordinate transformation and coordinate to do with this algorithm.)

Simple vhdl description to show numbers on 7-segment s on Altera DE2 board.

verilog编写的程序实现三八译码器功能，输入为3位，输出为8位，实现选择的功能。 verilog编写的程序实现三八译码器功能，输入为3位，输出为8位，实现选择的功能

用verilog语言写的简单的键盘扫描代码，适合初学者，用alter的软件编写的程序代码。(Using verilog language to write simple keyboard scan code, suitable for beginners, with alter software program written code.)

一个精确时钟的v-log程序，只用一个全局时钟，增加了精确度(An accurate clock in the v-log program, only one global clock, increased accuracy)

利用xilinx开发板，使用嵌入式系统，编写的ps2键盘和利用dds原理产生正弦波的程序(Using xilinx development board, the use of embedded systems, the preparation of the ps2 keyboard and use the procedures dds elements of the sine wave)

说明：  In the data management system a significant role of the Data link layer is to convert the unreliable physical link between reader and tag into a reliable link. Therefore, the RFID system employs the Cyclic Redundancy Check (CRC) as an error detection scheme. In addition for reader to communicate with the multiple tags, an anti-collision technique is required. The technique is to coordinate the communication between the reader and the tags. The common deterministic anti-collision techniques are based on the Tree algorithm such as the Binary Tree and the Query Tree algorithms.

ad9850函数发生器 MSP430单片机驱动程序 扫频 DDS(AD9850 DDS)

该文件.RAR它有关的4加法proyect - 位这proyect使用，以12和4列，为您proyect。

这个是vhdl中很常见的jk filpflop的文件只用于很小数位的变化 其中的jk文件是up down运算都符合的(This is a very common vhdl jk filpflop file is only used for very small changes in a digital file which jk is up down operations are met)