SDH接收处理

单片机和FPGA的通信程序，发送5个数，传输稳定，可以自行修改可一次传多个数(MCU and FPGA communication program, send five the number of stable transmission, you can modify the number may be more than one pass)

basic cpu design in verilog

this Code is in verilog HDL. This Code is for piplined processor with 4 opcode. this will work in three cycle latch, decode and exicute.. test bench for xilinx ise is laos given

一共7篇文章，介绍了使用fpga产生任意分布白噪声的方法，值得借鉴(A total of seven articles, describes using fpga to generate arbitrary distribution of white noise, it is worth learning)

stc12c5a60s2单片机做的两路呼吸灯，可以用ad和按键控制闪动频率(stc12c5a60s2 SCM done with the two breathing lights, you can use the ad and buttons to control the flashing frequency)

ldpc编码器ru算法的verilog语言的完整实现，希望对您有用(ldpc encoder, RU, VERILOG，altera)

详细的说明了FPGA设计的整个流程 FPGA设计全流程Modelsim>>Synplify.Pro>>ISE-Detailed description of the FPGA design flow of the entire FPGA design flow full Modelsim> > Synplify.Pro> > ISE

read data of type character from flash memory

标准的异步串口通讯设计程序――基于VHDL编程-communication design programme of standard asynchronous serial port base on VHDL programme

An universal shift register performs the following tasks load, right shift ,left shift and parallel load as the selection inputs are 00,01,10,11 respectively. Such a register is implemented here in Quartus.