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Interleaver
基于FPGA实现交织 在通信中交织的算法 已在板上通过测试(based on FPGA to Interleaver)
- 2018-02-01 20:54:13下载
- 积分:1
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卡内基梅陇大学verilog课程讲义-unlocked
verilog讲义
卡内基梅陇大学verilog课程讲义-unlocked
卡内基梅陇大学verilog课程讲义-unlocked(Verilog Course Lectures at Carnegie Mellon, University Verilog Course Lectures at Carnegie Mellon University Verilog Course Lectures at Carnegie Mellon University)
- 2020-06-20 18:00:02下载
- 积分:1
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BOOTH
基于BOOTH的32位快速乘法器的设计源码-BOOTH-based 32-bit fast multiplier design source
- 2022-02-16 09:50:44下载
- 积分:1
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FPGA
基于FPGA的VHDL编程实现各种音频信号,采用的是周立功公司的fusion_startkit开发板。-FPGA-based VHDL Programming realize a variety of audio signals, are used by companies fusion_startkit weeks Ligong development board.
- 2022-07-15 20:29:13下载
- 积分:1
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QuartusII
基于QuartusII环境下以模块化的形式做成的视频复合同步信号。-QuartusII-based environment to create the form of modular composite video sync signal.
- 2022-03-03 23:44:07下载
- 积分:1
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串uart的vhdl,verilog,lattic实现原码
里面有四个文件,分别UART 源码 (lattice version)uart 源码 (Veri...
串uart的vhdl,verilog,lattic实现原码
里面有四个文件,分别UART 源码 (lattice version)uart 源码 (Verilog)uart 源码 (VHDL)uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice version) uart source (Verilog) uart source (VHDL) uart16550.tar
- 2022-04-12 23:45:53下载
- 积分:1
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- 2022-01-26 03:14:33下载
- 积分:1
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transmittermegafunction
lvds transmitter megafunction (lvds transmitter megafunction)
- 2008-03-09 19:40:03下载
- 积分:1
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m_ca7
verilog编写的基于CA算法的m序列发生器,其中验证了多种CA系数来实现m序列。(CA-based algorithm written in verilog m-sequence generator, which verify the CA factor to achieve a variety of m-sequence.)
- 2011-10-26 14:33:59下载
- 积分:1
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本章介绍了两个EDA技术的综合应用设计实例:数字闹钟和直接数字频率合成器DDS。...
本章介绍了两个EDA技术的综合应用设计实例:数字闹钟和直接数字频率合成器DDS。-EDA chapter describes the two technologies integrated application design example: digital alarm clock and direct digital synthesizer DDS.
- 2023-07-23 01:50:04下载
- 积分:1