几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码

改VHDL代码可以实现超声波测距的功能，其精确度达到US级，可以用七段数码管显示其数值(sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging )

sender的verilog 利用fpga实现-sender using the Verilog FPGA realize

一个具有“百分秒，秒，分”计时功能的数字跑表，可以实现一个小时以内的精确至百分之一秒的计时。 数字跑表的显示读者可以通过编写数码管显示程序来实现，本训练只给出数字跑表的实现过程。 读者还可以通过增加小时的计时功能，实现完整的跑表功能。(A " percentage of seconds, seconds, minutes," digital stopwatch timer can be achieved within an hour of precision to the hundredth of a second time. Digital stopwatch readers can display the digital display through the preparation of procedures to achieve, given the training is only the realization of the process of digital stopwatch. Readers can also function to increase hours of time to achieve full stopwatch function.)

先用Matlab理论仿真，再用Verilog语言在ISE环境下编写程序，可通过手机发送指令来控制上下变频器的参数。(Firstly, we use the theory of MATLAB to simulate, and then use Verilog language to write programs in ISE environment. The parameters of up-down converter can be controlled by sending instructions from mobile phone.)

本人初学VHDL时编的比较系统的VHDL源程序 巨实用 -I am learning more systematic series of practical VHDL source Giant

这是在 vhdl 的简单循环的拳头在后进先出队列。缓冲区的大小和数据大小可以通过 N 和 W 的参数配置。队列最前面的是可用输出数据。两个信号控制写入和读取数据。如果缓冲区是空的还是满的两个输出信号信息。

verilog描述的实用消抖电路，采用三个D触发器和一个JK触发器。使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏(verilog description of the practical elimination shake circuit, using three D flip-flop and a JK flip-flop. Prepared source files using the emacs , iverilog simulation adopted, within the simulation images png screenshots)

说明：  高速宽带数字调制技术的研究，该论文也是非常经典的，希望对大家有帮助(High-speed broadband digital modulation technology, the paper is also very classic, I hope all of you help)

大名鼎鼎的Synopsys公司出的8051IP Core VHDL语言编写，能被keilC51支持-famous Synopsys Core 8051IP the VHDL language, can be supported keilC51

用verilog实现的buffer，经过了fpga平台验证。(Implement buffer with verilog.)