几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码

这是基于Nios II的12864液晶点亮程序，包含汉字、字符等(This is a program which is based on Nios II ,its function is light the 12864 LCD that including Chinese characters, characters)

基于单片机的DDS信号发生器，具有DDS思想的单片机编程。。。(Sunplus based DDS signal generator with DDS thinking microcontrollers. . .)

说明：  基于FPGA，用verilog hdl语言实现串口收发实验(Based on FPGA, using Verilog HDL language to achieve serial port transceiver experiment)

vhdl random numbergenerater

数字ic设计，二级缓存，格雷码，深度256，(Digital IC design, two level cache, gray code, depth 256.)

AVR IP CORE 可以直接用于工程的开发和 已经通过编译和仿真-AVR IP CORE can be directly used for project development and has passed the compiler and simulation

TD-LTE中（3.1.7）咬尾卷积码编码器verilog代码(Tail-biting convolutional code encoder verilog code)

这是一个二进制的最简单分频器，是一个简短的fpga代码，用verilog书写(This is the most simple of a binary frequency divider, the fpga is a short code, written in verilog)

实现fpga 读写flash 在k7上验证(Realization of FPGA read-write flash verification on K7)

说明：  VGA图像显示，可实现图片和实现移动功能(VGA image display, enabling images and moving functions to achieve)