几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码

TASKS OF TWO TYPES CAN BE RUN FOR EVERY 2 MIN.

四位除法器的VHDL源程序-four division of VHDL source

一种新的FIFO实现方法,verilog描述，通过modelsim 6.0 仿真，Quartue综合-FIFO realize a new method, verilog description, modelsim 6.0 through simulation, Quartue integrated

比较详细的阐述了图像压缩的原理,并基于DSP和VHDL实现该系统,最后在FPGA上通过.(More detailed exposition of the principles of image compress, and VHDL-based implementation of the system, and finally in the FPGA.)

generate sine wave. Inputs : Amplitude, phasein, frequency

用veriolg 语言编写的串口通讯程序，通过FPGA控制串口的通讯。(a veriog program completed on FPGA to contrlo a uart to communicaton with a computer )

基于FPGA的JPEG图像压压缩，实现JPEG图像的实时压缩 (Real-time compression pressure compressed FPGA-based JPEG images, JPEG images)

LCD 驱动的IPCORE，可用于alteraFPGA(LCD driver IPCORE, can be used to alteraFPGA)

verilog编写的alu模块-Verilog modules prepared by the ALU

XAPP224 VHDL Data Recovery design file