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formal_verification
说明: 现在最流行的RTL设计方法之一,本书为全球流行的设计入门书籍(One of the most popular RTL design methods nowadays, this book is an introductory book for popular design all over the world.)
- 2020-06-23 22:00:02下载
- 积分:1
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Implementing a TMDS Video Interface in the Spartan-6 FPGA
This application note describes a set of reference designs able to
transmit and receive DVI and HDMI data streams up to 1080 Mb/s using the
native TMDS I/O interface featured by Spartan-6 FPGAs.
- 2022-10-21 19:25:03下载
- 积分:1
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problem
在学习verilog 中与遇到一些列问题的整理。(this Documentation is about the problem about verilog which is meeted when i was learn FPGA)
- 2014-03-07 22:24:19下载
- 积分:1
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gtx_aurora_zc706_clock_module
对aurora模块时钟处理模块,实现时钟的分频等处理(Aurora module clock processing module,Clock frequency division and other processing)
- 2018-01-23 09:03:31下载
- 积分:1
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Verilog数控分频器的设计
分析参考代码中的各语句功能、设计原理、逻辑功能,根据图1的波形提示,编写相应的Testbench文件代码,并用Modelsim进行仿真(仿真可以跳过时钟分频到100hz进程)。
在此基础上进行硬件验证。实验方法为:将clk接20Mhz时钟信号,rst_n接核心板开关S1,fout接发光二极管SD0,预置值d从DKA0-DKA7输入,改变d的输入,从发光二极管SD0判断输出信号的频率。
- 2022-11-07 09:25:04下载
- 积分:1
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shumaguandongtai
VHDL的动态扫描显示六个数码管,包含分频代码产生25kHz的扫描信号作为时钟。(VHDL dynamic scanning display six digital tube contains 25kHz scanning signal is generated as a clock divider code.)
- 2012-11-26 14:40:42下载
- 积分:1
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turbo_encode
turbo码的编码程序,verilog HDL,在ISE环境中(turbo code encoding process)
- 2014-03-29 15:09:58下载
- 积分:1
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PipelineCPU_5stage_verilog
管道 CPU 与 5 阶段: 如果、 ID EX MEM,WB。每个模块都有一台试验。它包含一个整个的 ISE 项目。您可以直接运行它。ROM 模块已预先存储指令作为一个实例。
- 2022-07-17 12:45:49下载
- 积分:1
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AD9250 204b Verilog源码
说明: AD9250是一款双通道14位ADC,最高采样速率250 MSPS,JESD204B Subclass 0或Subclass 1编码串行数字输出(The ad9250 is a dual channel 14 bit ADC with a maximum sampling rate of 250 MSPs and jesd204b sub class 0 or sub class 1 coded serial digital output)
- 2021-04-14 11:01:55下载
- 积分:1
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pc104vhdl_change
PC104总线的CPLD代码,调试已经通过,可以修改应用到其他的工程(PC104 bus CPLD code, debugging has been passed, you can modify the application to other engineering
示例用法:)
- 2013-08-29 12:07:43下载
- 积分:1