Implementing a TMDS Video Interface in the Spartan-6 FPGA

单周期CPU，Verilog源码，                                              解压即可运行。

实现千兆以太网数据发送，通过GMII接口向PHY写数据，控制PHY发送数据。(Implementation of Gigabit Ethernet data transmission, write data to the PHY through the GMII interface, control PHY data.)

VERILOG HDL pid算法 带仿真验证(pid by verilog HDL)

time to digital convertor

自己搜集的一些FPGA指南教程，包括一些高工们的经验之谈、设计原则，目前正在学习，有一定帮助，分享给大家(Gather their own of some FPGA guide tutorial, including some senior engineers are the voice of experience, design principles, are learning to have some help, to share to everyone)

三层电梯的详细电路 Foundation版 包括强行开关门打断(Elevator control Foundation project)

可实现两个4bit补码的加法及减法，有溢出提示(adder with overflow hint)

基于FPGA的视频图像加密系统 DE2_70+TRDB—D5M+VGA(FPGA-based video encryption system DE2_70+TRDB-D5M+VGA)

关于一个串行数据输入 根据时序将数据分两路输出的程序 (on a serial data input timing will be based on output data using two procedures)

UART功能,可以增加在NIOS2內,主要來做外部Flash的擦除及寫入,需搭配上位機傳輸字串來控制(UART function, can increase the NIOS2, the main external Flash to do the erase and write, to be a string with the host computer to control the transmission)