计数器的VHDL代码

Quartus2环境下基于VHDL状态机的交通灯程序(VHDL state machine traffic lights based on Quartus2 environment)

浙江大学体系结构实验课代码，5级流水线实现旁路和停顿(5-stage pipeline to achieve realization of the bypass pipeline bypass pause 5 pause)

Verilog HDL编写的串并转换。采用iout类型口。包含源文件和测试文件。用Modsim编译。-Verilog HDL Series and the preparation of the conversion. I used iout types. Includes source and test papers. Modsim compiler used.

四位动态数码管显示数字时钟的分位和秒位。工具：Quartus ii 6.0 语言：VHDL-4 shows the number of dynamic digital tube digital clock and seconds bit. Tools: Quartus ii 6.0 Language: VHDL

用Verilog语言实现的FPGA UART独立收发模块 思路简单，代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond. 功能：串口收到数据后立即回传，此后每一秒串口数据+1再发送。(Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA VERSA verified by the compiler Lattice Diamond. Features: Serial data is received immediately after the return, then every second serial port and then send the data+ 1.)

从MIC输入一段音频然后，再从AOUT的接口播放出来的verilog 的代码-Input from the MIC for some audio and then AOUT interface from broadcast in the Verilog code

本文首先对多功能车辆总线的基本原理进行了简要的概述，接着对其实时协议进行了分析，然后对 MVB2 类设备控制器的功能及其功能模块的划分设计进行了详细的分析；最后对各功能模块进行了编程实现，并给出了仿真验证波形。(Firstly, the basic principle of the multifunction vehicle bus are briefly outlined, then analyze the real time protocol, then carried out a detailed analysis of the classification of the design function and the function module of the MVB2 device controller; finally, the function of each module of the program, and gives the simulation waveforms.)

说明：  使用DE2实现DDS，步骤简单，配置管脚可自查看(Using DE2 to realize DDS, the steps are simple and the pins can be self-checked.)

用VERILOG编写的VGA字符显示，可以在电脑屏幕上显示字符,已通过测试(Prepared with the VERILOG VGA character display, can display characters on a computer screen, has been tested)

说明：  简单uart，verilog语言编写，已经经过测试，有需要的可以看看(Simple uart, Verilog language, has been tested, you can see if you need it)