篮球24秒可控计时器设计

介绍专用集成电路设计的一本书，很有参考价值，适合高年级本科生和研究生(Introduction ASIC design a book, a good reference for senior undergraduate and postgraduate)

Xilinx FPGA using leftover multipliers and block RAM

用VERILOG实现自动售货机功能，运行正确，希望有帮助(Use VERILOG implementation vending machine function, correct operation, hope to have help)

该源代码是RS（31，19）码的完整编译码程序，采用的是VerilogHDL语言，包含了RS码的编码和译码，这蛋疼的东西花费好多时间(The source code is RS (31,19) code complete encoding and decoding procedures, and spend a lot of time using is VerilogHDL language contains the encoding and decoding of RS codes, this egg pain)

FPGA的仿真实例，Verilog代码编写，过程详尽，代码易懂。第三个文档-FPGA simulation examples, Verilog coding, the process in detail, code easy to understand. The third document

altera max10 USB demo，使用了phy，把开发板配置成U盘模式(altera max10 USB demo，using PHY device，design a U pan)

实现了QPSK的调制，使用了ise自带的dds的IP核(QPSK is modulated and the IP core of DDS is used in ise.)

一个基于FPGA的数字跑表系统的设计，最小单位是百分表位。采用十进制进位。-FPGA-based digital stopwatch system design, the smallest unit is a digital dial indicator. Binary using the metric system.

买的Altra公司的一款Max II EPM1270T144的电路板，其中的一个用Verilog HDL 编写的驱动数码管的程序，完全可用。-Altra Inc. bought a Max II EPM1270T144 circuit board, one written in Verilog HDL using the digital controls process-driven, fully available.

VHDL拔河电路的设计 基于cyclone V  VHDL拔河电路的设计 基于cyclone V VHDL巴赫电路的设计 基于cyclone V VHDL巴赫电路的设计 基于cyclone V VHDL巴赫电路的设计 基于cyclone V