布斯算法结构的 VHDL 代码

电子闹钟：基于fpga的电子闹钟设计，采用模块化方式-Electronic alarm: FPGA-based electronic alarm clock design, modular approach

offset_cancellation code for matlab to hdl

这是一本关于verilog编程语言的教程,对学习verilog语言有帮助-This is the one on the Verilog programming language tutorial, Verilog language learning has helped

thesis for simple virus detection processor which is developed in xilinx

verilog实现的FPGA三态以太网链路层通信代码，里面有状态机，并按各个模块的功能分了文件夹，还有说明文档，自定义帧的产生和接收，开发环境为Xilinx ISE，测试无误。(verilog realization FPGA Tri-Mode Ethernet link layer communication code, which the state machine, according to the function of each module sub folder, as well as documentation, self-defined frame generation and reception, the development environment for the Xilinx ISEtest and correct.)

这是一个AMBA APB桥实现VHDL。这包括主人，奴隶和试验台试验桥。我已经测试功能。

用VHDL语言仿真音乐设计 用VHDL语言仿真音乐设计-Simulation using VHDL language music design music design simulation VHDL language

d5m的DE2驱动Verilog HDL (d5m driven on DE2 by Verilog HDL )

Verilog的应用例程，包含了基本的硬件编程，加法器，触发器(Application of Verilog routines, including the basic hardware programming, adders, flip-flop)

本源码为Nios II的开发示例,主要演示Nios II的定时中断器的应用。开发环境QuartusII。 本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of an example, the main demonstration Nios II interrupt timing device applications. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.