布斯算法结构的 VHDL 代码

wishbone 源代码，opencore-wishbone source code, opencore

使用FPGA实现三相直流无刷电机换相，该程序可以使用(Use FPGA to realize the three-phase brushless DC motor commutation, the program can use)

说明：  一个编码解码系统，其中包含一个信号发生器（用查找表方式实现）、一个m序列生成器（用来编码和解码用）、一个FiFo队列用来做缓存以及用串口方式进行收发读取数据。(An encoding and decoding system, which includes a signal generator (implemented by look-up table), an m-sequence generator (used for encoding and decoding), a FIFO queue for caching, and a serial port for receiving, transmitting and reading data.)

sd_sdram_lcd 是读取SD卡中的数据，然后通过LCD显示(It is to read the data in SD card and display it by LCD)

说明：  SDIO 接口，实现SD卡的控制器功能，带有详细的注释(SDIO Interface,to realize the controller of SD Card,and have detail description.)

时钟在单片机中的应用，用于控制中断及显示程序(Clock in the MCU application, used to control interrupt and display program)

一个简单的UCOSII操作系统，在DE2上面调试通过(A simple UCOSII operating systems, debugging through the DE2 above)

reed-solomon译码器。共有7个文件，分别为译码器的7个模块。-reed-solomon decoder. A total of seven papers, respectively, the decoder module 7.

stepper motor vhdl pin assignments and code

24秒倒计时系统（有跑马灯） 利用CPLD-24 seconds remaining systems (5,250) using CPLD