6通道正弦波发生器，产生频率，相位，幅值都可调的正弦波形...

高级verilog编程实现讲义，全英文讲义 -Senior verilog programming lecture notes, handouts in English

FPGA的仿真实例，Verilog代码编写，过程详尽，代码易懂。-FPGA simulation examples, Verilog coding, the process in detail, code easy to understand.

231卷积码的verilog实现，前面是详细的文档说明，有源程序，绝对原创！！！！(Verilog achieve 231 convolutional code, preceded by a detailed description of the document, the source, the absolute originality! ! ! !)

verilog编写的计算百分比模块-Verilog prepared by calculating the percentage module

vhdl的仿真 quartus 2的flv视频 -VHDL simulation of the flv video quartus 2

本例程位于 VMD642_CPLD目录中。 使用 CPLD 实现辅助译码、LED 指示灯控制、看门狗等各种逻辑控制电路。源程序使 用 Verilog HDL书写，编译开发系统使用 Cypress公司的 Warp 6.3。(This routine is located VMD642_CPLD directory. Using CPLD implementation auxiliary decoding, LED indicator control, watchdog, and other logic control circuitry. Written using Verilog HDL source code, the compiler development system using Cypress' s Warp 6.3.)

说明：   基于VHDL语言数字秒表设计,在FPGA实验平台下开发(Digital stopwatch design based on VHDL, FPGA experimental platform under development)

report for a report for a class

低通滤波器（由matlab和simulink两种方法实现）源文件及图片示例(Low-pass filter) source file and photo examples (by the two methods matlab and simulink)

在硬件方面十进制到二进制将不需要采用加法器计算的方式，大大减少了计算时间。