DDS_Dual_ports Verilog实现

在黑金AX7103板子上（A7）实现的demo工程中，存在一些bug。给与修正

国外大学上课用PPT。关于乘法器架构，实现，优化，有booth算法的具体实例。(Foreign university classes PPT. About multipliers architecture, implementation, optimization, there is a specific instance of the booth algorithm.)

加减可控制的十到十六进制计数器。完全准确，可以放心使用的(Add and subtract controllable ten to hexadecimal counter. Entirely accurate, can be at ease of use)

EKG SIGNAL PROCESSING THROUGH CORDIC

小波包分解，重构轴承振动信号，Hilbert包络，FFT进行频谱分析，以获得轴承故障频率。(Wavelet packet decomposition, reconstruction of bearing vibration signal, Hilbert envelope, FFT spectrum analysis to obtain the bearing fault frequencies.)

说明：  Verilog 黄金参考指南是 Verilog 硬件描述语言及其语法 语义 合并以及将它应用到硬件设计的一个简明的快速参考指南。(Verilog Golden Reference Guide is a concise and fast reference guide for Verilog Hardware Description Language and its syntax and semantics merging and its application to hardware design.)

(A good set of learning information for Verilog timing chapter, with source code and engineering documents, you can follow the tutorial self-study)

1602是目前最常用的显示器件，本例是通过verilog 代码实现1602的显示(1602 display)

一个8位的CPU设计，用verilog语言写的，希望有用(A CPU OF 8 BITS )

数字滤波器组。包含matlab程序和word说明。通过一个低通数字滤波器和多个带通数字滤波器组合成一个滤波器组(Groups of the digital filter. Contains matlab program and word description. Through the combination of a low pass digital filter, and a plurality of band-pass digital filter into a filter bank)