protel中fpga封装库3，非常难找的

多个MATLAB设计滤波器的方法程序以及图形实现(number MATLAB filter design methods and procedures and Graphics)

vhdl code fpga for lcd 2*16

说明：  实现24小时计时，因为位数不够，这里是12进位，可自行调整进位数(Realize 24-hour timing, because the number of digits is not enough, here is 12 carry, you can adjust the carry number by yourself.)

该程序用来实现电话计时以算取费用，比较简单(telephone cost metering verilog code)

四轴动力模块，用一个顶模块控制，输入有：油门（20档）；指令；水平仪控制指令，4个输出口(Axis power modules, with a top module control inputs are: accelerator (20 files) instruction Level control instructions, four output ports)

MATLAB to HDL Code conversion

6级流水，verilog实现浮点数的加法，其中浮点数格式符合IEEE754标准-6 water, verilog realize the floating point adder, in which floating-point format in line with the IEEE754 standard

60进制减法 相比较 代码效率高 可以进行级联-60 compared to 229 subtraction efficient code can be concatenated

block-LDPC 译码VHDL 源代码(block-LDPC decode VHDL source)

Opencore的IP Core，有实际合成过，可以用，大家参考-Opencore of the IP Core, there is a practical synthesis that we could use, we refer to see