protel中fpga封装库3，非常难找的

基于ATEREAL EPM1270T144C5N CPLD 压力传感器数据采集原码 开发软件 Quartus II -ATEREAL EPM1270T144C5N CPLD-based pressure sensor data acquisition source Quartus II development software

说明：  关于一个8位处理器的分析，和源代码，VHDL语言设计，经过测试(on an eight processors, and source code, VHDL design, the test)

掌握SDRAM数据读写、刷新、初始化以及FPGA串口收发时序，熟练FIFO IP核的生成和调用。(Master SDRAM data read and write, refresh, initialization and the timing of sending and receiving of the serial port of the FPGA, skilled in the generation and invocation of the FIFO IP core.)

应用背景VHDL  ；CPU设计...................................................................................................................................................................................................................................................................................................................................................................关键技术VHDL  ；CPU设计...................................................................................................................................

用Verilog HDL编写的PID程序代码，成功调试，运行良好。(The source code of PID in Verilog HDL.Simulation was successful.)

在 VHDL 中实现的游戏 实施LFSR创建与随机游戏板 随机颜色。使用VGA控制器和块内存 我们显示游戏板，并写入它取决于某些规则。用户 可以控制如何密游戏板填充，则显示什么颜色， 而如何快速模拟。

Implementation of Serial Infrared decoder for low-speed IrDA communications.

4X4电子密码锁的中央控制系统。控制6位输入。-4x4 electronic locks central control system. Six input control.

USB设备接口的驱动程序，采用verilogHDL语言编写，并包含相关说明资料(USB device driver interface, using verilogHDL language, and contains descriptive information)

异步FIFO的实现，很经典的三段式状态机的写法。(The realization of the asynchronous FIFO, very classic three-step writing state machine.)