Cyclone-V-GX-开发板原理图-(5CGXFC5C6F27), Audio,HDMI 部分Demo

时钟分频代码，PWM产生 RTL 源代码。(clock divider，PWM generator RTL Source Code)

一种基于CPRI标准的WCDMA NoddeB射频光纤拉远接口FPGA设计.pdf (CPRI compliant the WCDMA NoddeB RF fiber pull far from the interface of the FPGA design. Pdf)

实现24小时计时，因为位数不够，这里是12进位，可自行调整进位数(Realize 24-hour timing, because the number of digits is not enough, here is 12 carry, you can adjust the carry number by yourself.)

维特比译码器，调用IP核，软判决输入，开发平台Xilinx Spartan-6系列FPGA(viterbi decoder, using IP core resource, soft decision input,develop platform is Xilinx Spartan-6 series FPGA)

EDA/VHDL数字频率计，可编程逻辑门阵列，EDA课程设计(EDA/VHDL digital frequency meter, programmable logic gate array, EDA curriculum design)

VHDL 2FSK调制解调器各部分的原理与代码(The principle and code of each part of the VHDL 2FSK modem)

verilog编写的基于CA算法的m序列发生器，其中验证了多种CA系数来实现m序列。(CA-based algorithm written in verilog m-sequence generator, which verify the CA factor to achieve a variety of m-sequence.)

说明：  利用ISE编写的产生WALSH码的verilog程序，简单易懂，稍稍修改就可以产生出自己想的8 16 32 64位的WALSH码。。(Prepared using ISE verilog code generated WALSH procedures, easy to understand, a little modification can generate their own like the 8,16，32，64-bit code WALSH. .)

本程序使用verilog编写的DES程序，结构清晰明了，资源占用少，希望学习此算法的程序猿能多多评价，大家的评价才是我更好写程序的动力，谢谢大家！

System Verilog decodificator. Enters a value(binary), drops hundreds, tens and units in BCD