阿尔特拉 发动机控制器 示例

应用背景使用ise10.1，verilog硬件语言，基于Spartan3的开发。模拟汽车转向灯。拨动开关，led灯依次循环点亮。关键技术拨动左开关，led灯向左依次循环点亮。拨动右开关，led灯向右循环点亮。使用的语言是verilog，基于ise10.1平台，是数字电路逻辑设计的应用

应用背景i2cSlave is a minimalist I2C slave IP core that provides the basic framework for the implementation of custom I2C slave devices. The core provides a means to read and write up to 256 8-byte registers. These registers can be connected to the users custom logic, thus implementing a simple control and status interface.关键技术The core has up 256 registers that can be accessed via I2C. I2C write operations are used to set the register address pointer, and write the register data. I2C reads are used to read the register data. Successive data reads or writes result in data being read or written from incremental register addresses. There is no limit on how much data can be read or written in a single access, but the internal register address pointer will wrap round to 0 once it reaches 255. Note that the address pointer is not initialized at reset, and the address pointer must

对pci9054芯片的配置进行了设置，并对PCI9054的各状态机进行了设置，程序经过了测试(Pci9054 chip on the configuration of the set, and each state machine PCI9054 been set, the program have been tested)

基于网口的收发数据及解析数据内容的verilog代码实现(Based on the Internet port to send and receive data and parse the contents of the data verilog code)

用流水线的方法实现16位乘法器，运算速度快，消耗时钟资源少(Pipeline method to realize 16-bit multiplier, which is fast in operation and consumes less clock resources)

基于Verilog的自动售卖机设计，利用数码管显示商品价格和找零，用LED灯的量灭表示选定的商品，用按键（按键设置了消抖模块）控制确认购买和选择和找零，购买并找零后重新跳回IDLE重新选择商品。

ram 的ahb接口，ram ahb interface 好用的中转接口ram 的ahb(ram ahb interface ram ahb interface ram ahb interface)

在FPGA上实现的图像处理中值算法，其中包含对输入数据的控制，内容详细，如果需要复杂的 图像滤波算法只需要修改中值模块即可。在altera上可用，如果要再xilinx上使用，只需要将fifo替换即可

nios学习资料，fpga调用外部sdram实例，值得初学者下载。(nios learning materials, fpga call external sdram instance, it is worth beginners to download.)

基于Xilinx Vertex2的可综合的2048x10位的读写可控制FIFO模块源代码，深度可控(Based on the Xilinx Vertex2 can be integrated 2048x10-bit read and write can control the FIFO module source code, the depth of controllable)