阿尔特拉 发动机控制器 示例

一种十字路口交通灯在matlab环境中的实现源码(Traffic lights at the crossroads)

无线发射模块的 SRRC 成型匹配滤波设计 Verilog 代码，包含了所有测试，主模块，可以用在基带调制端，滤波器的滚降系数0.10～0.25，如果那些没有做过这方面的朋友，可以看看实现，和方法，提供一个参考和帮助

有三个基于FPGA驱动高速AD/DA的程序、硬件电路图、使用向导手册、连接方法，支持ADDA_AX301，ADDA_AX415，ADDA_DB2C8，可以下载到 FPGA 黑金开发板、FPGA 黑金开发板学生版结合相关模块进行使用，

主要编写了一组二进制数据通过根升余弦滤波器后的波形，但并没有使用ISE内部的FIR滤波器内核，该程序相当于编写了一个根升余弦滤波器。(Mainly prepared a set of binary data through the root raised cosine filter waveform after, but did not use the ISE internal FIR filter kernel, the program is equivalent to the preparation of a root raised cosine filter.)

步进电机定位控制系统，VHDL程序，里面有注释(Stepper motor position control system, VHDL program, there are comments)

1、PC和寄存器组使用时钟触发。 2、指令存储器和数据存储器存储单元宽度一律使用8位，即一个字节的存储单位。 3、控制器部分可以考虑用控制信号真值表方法（有共性部分）与用case语句方法逐个产生各指令其它控制信号相配合，注意：信号必须与状态配合。。当然，还可以用其它方法，自己考虑。 4、试用的汇编程序，而且必须包含所要求的所有指令。Slt、sltu指令必须检查两种情况：“小于”和“大于等于”；beq、bne指令必须检查两种情况：“等”和“不等”。这段汇编程序必须尽量优化，同时，给出每条指令在内存中的地址。(1, PC and register groups are clocked. 2, the command memory and data memory storage unit width will use 8 bits, that is, a byte storage unit. 3, the controller part can be considered with the control signal truth table method (common part) and with the case statement method to produce each command other control signal match, Note: the signal must be with the state. The Of course, you can also use other methods to consider their own. 4, try the assembler, and must contain all the required instructions. Slt, sltu instruction must check two cases: "less than" and "greater than or equal to"; beq, bne instruction must check two cases: "wait" and "unequal". This assembler must be optimized as much as possible, giving the address of each instruction in memory.)

说明：  Actel 8051 Verilog core

设计一个十进制计数器，具有显示位置随计数时钟在八个数码管中左右滚动的功能。(Design of a decimal counter, a display position with the count clock in at around eight digital scrolling function.)

《Altera FPGA_CPLD设计 高级篇》详细介绍FPGA应用于高级特性，LogicLock设计，时序约束，设计优化，高级工具及系统级设计技术，是深入学习FPGA的重要材料(" Altera FPGA_CPLD advanced part design" details FPGA used in advanced features, LogicLock design, timing constraints, design optimization, system-level design tools and advanced technology, in-depth study is an important material for FPGA)

xilinx的时序约束实验，通过阅读本文档，你可以用全局时序约束来轻松提高已有的项目的系统时钟频率，同时你还可以用映射后静态时序报告以及布局布线后静态时序报告来分析你的设计性能(Xilinx timing constraints of the experiment, by reading this document, you can use the overall timing constraints to easily enhance existing projects the system clock frequency, at the same time you can also use static timing report after mapping, as well as after placement and routing static timing analysis report to you design performance)