-
qpsk_demod_use_FPGA
根据软件无线电的思想,提出了一种新颖的数字信号处理算法,对QPSK信号的相位进行数字化处理,从而实现对QPSK信号的解调.该算法允许收发两端载波存在频差,用数字锁相实现收发端载波的同步,在频偏较大的情况下,估算频偏的大小,自适应设置环路的带宽,实现较短的捕获时间和较好的信噪性能。整个设计基于XILINX公司的ISE开发平台,并用Virtex-II系列FPGA实现。用FPGA实现调制解调器具有体积小、功耗低、集成度高、可软件升级、扰干扰能力强的特点,符合未来通信技术发展的方向。(According to the idea of software radio, a novel digital signal processing algorithm, the phase of QPSK digital signal processing, enabling the demodulation of QPSK signals. This algorithm allows the sending and receiving ends of the carrier frequency difference exists, using digital phase-locked to achieve synchronization of sending and receiving end of the carrier, in the case of large frequency offset, frequency offset estimation of the size, adaptive set the loop bandwidth to achieve shorter acquisition time and better noise performance. The whole design is based on the company XILINX ISE development platform, and Virtex-II series with the FPGA. FPGA realization of a modem with a small size, low power consumption, high integration, software upgrades available, the characteristics of strong interference interference, in line with the future direction of ICT development.)
- 2010-12-06 10:52:36下载
- 积分:1
-
Y312448.zip
基于VHDL的SDH专用芯片的TOP-DOWN设计,
内有全套源码以及图片,内容详尽,绝对真实可靠!(VHDL based on the SDH ASIC Design TOP-DOWN, which has a full set of source code, as well as pictures, and detailed, reliable and absolutely true!)
- 2008-05-12 19:21:03下载
- 积分:1
-
简单的CPU(源代码和合成脚本)
应用背景此文件包含所有的源代码和脚本,以Altera公司的简单CPU的合成。500MHz时钟设计运行。 ;关键技术使用CLA提高速度的设计。这只是一个简单的CPU,它的结构很简单,它没有任何管道或类似的东西。
- 2022-04-30 14:14:37下载
- 积分:1
-
ahb_sramc
基于AHB总线的sram控制器,带有memory bist(SRAM controller based on AHB bus)
- 2018-05-19 20:47:28下载
- 积分:1
-
percent
verilog编写的计算百分比模块(Verilog prepared by calculating the percentage module)
- 2005-03-08 21:33:38下载
- 积分:1
-
6502原码
6502原码,即视频编码方面的代码,对初学者有好处,大家喜欢的话记得顶一下哈,好不容易才能弄个出来啦的
- 2022-12-17 15:25:04下载
- 积分:1
-
sanjose_hdlcon
FFT implementation using C program
- 2014-02-11 21:01:40下载
- 积分:1
-
11_rs485_uart_top
说明: verilog编写的RS485读写驱动程序(RS485 read-write driver written by Verilog)
- 2020-03-08 12:28:10下载
- 积分:1
-
Door opener
模块规格:门通过滑动打开。每侧都有一个红外线传感器和一个光电管。如果有人靠近门,传感器会向芯片发送信息。电动机将可由传感器切换的门向两个方向移动。如果门受到障碍物的阻碍,则电动机的电流会升高。在这种情况下,系统会收到反馈,如果门完全打开或关闭,则结束该过程。如果这个标志在门关上的时候出现(有人或有什么东西被门包围了),它会迫使门完全打开。过了一会儿门又想关上。系统也可以手动切换(打开或关闭)。
- 2022-08-14 21:05:23下载
- 积分:1
-
cla - Copy
说明: ADDER USING VERILOG ADDER WITH VERILOG VERILOG ADDER
- 2019-03-19 01:35:37下载
- 积分:1