时序逻辑与组合逻辑（VHDL）

使用verliog设计实现LUT查找表乘法器，通过modelsim仿真验证通过(Designed and implemented using the LUT lookup table verliog multipliers, through simulation by modelsim)

将Verilog代码转换成C++代码的软件，C源代码。-soft for changing Verilog code to c++ code ,c code

HDLC接口协议的FPGA实现使用verilog-design of HDLC

常见的几种电机的特征与控制方法-Several common characteristics of the motor and control method

多进制数字频率调制(MFSK)系统VHDL程序-Multi-band digital frequency modulation (MFSK) system VHDL procedures

芯片ad0809与da0832的实现程序-ad0809 chip with the realization procedures da0832

用于FPGA的反Z变换算法的Verilog代码。可用于JPEG及MPEG压缩算法。-FPGA for the anti-Z transform algorithm of Verilog code. Can be used in JPEG and MPEG compression algorithms.

PCI的VHDL源码希望对大家有用！-PCI VHDL source hope useful for all!

用状态机对A/D转换器0809的采样控制电路的实现。工具：Quartus ii 6.0 语言：VHDL-State machine used for A/D converter sampling control circuit 0809 is achieved. Tools: Quartus ii 6.0 Language: VHDL

imp book for cmos technology