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32位元浮点数加法器,用于以VHDL编写的32位元CPU
32位元浮点数加法器,用于以VHDL编写的32位元CPU-32 bits floating-point Add
- 2022-10-08 15:20:02下载
- 积分:1
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testbench
说明: altera 最新的CYCLONE IV的pci-e核的testbench,VHDL源程序。(altera latest CYCLONE IV of the pci-e core testbench, VHDL source code.)
- 2010-04-22 10:20:24下载
- 积分:1
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Traffic-lights-at-the-crossroads
一种十字路口交通灯在matlab环境中的实现源码(Traffic lights at the crossroads)
- 2013-05-16 10:18:38下载
- 积分:1
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one_2017_v2
说明: 一个编码解码系统,其中包含一个信号发生器(用查找表方式实现)、一个m序列生成器(用来编码和解码用)、一个FiFo队列用来做缓存以及用串口方式进行收发读取数据。(An encoding and decoding system, which includes a signal generator (implemented by look-up table), an m-sequence generator (used for encoding and decoding), a FIFO queue for caching, and a serial port for receiving, transmitting and reading data.)
- 2021-03-15 18:24:40下载
- 积分:1
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vhdl-cordic-atan-master
Implementation of CORDIC atan block in VHDL
- 2019-05-14 16:51:26下载
- 积分:1
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SDRAM控制器源码,内含完整的控制器verilog源代码和测试代码,超值哈。...
SDRAM控制器源码,内含完整的控制器verilog源代码和测试代码,超值哈。-This readme file for the SDR SDRAM Controller includes information that was not
incorporated into the SDR SDRAM Controller White Paper v1.1.
- 2023-07-19 13:10:03下载
- 积分:1
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MUX
Multipleksor
3 to 1 - 3x1bit in, 1x1bit out
- 2013-09-18 16:21:25下载
- 积分:1
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fenpinqi de vhdlchengxu gongnengfnagzhen,政
分频器的VHDL程序,完整的建立工程,编译,功能功能仿真,验证-fenpinqi de vhdlchengxu gongnengfnagzhen,yanzheng
- 2022-02-21 21:03:34下载
- 积分:1
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yy
说明: 使用XILINX公司提供的板子里面的FFT的IP核,很好用(XILINX board provided the use inside the FFT of the IP core, useful)
- 2010-09-19 01:54:07下载
- 积分:1
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基于单片机与CPLD的 等精度频率计,VHDL语言
基于单片机与CPLD的 等精度频率计,VHDL语言-Based on SCM and CPLD
- 2022-11-25 20:35:03下载
- 积分:1