时序逻辑与组合逻辑（VHDL）

4 seg display, button debouncer, and controller for parking meter

verilog 写的 多功能数字钟-verilog to write multi-functional digital clock

EP2C5核心电路原理图，包括protel文件及其相应封装库-EP2C5 Core circuit Sch

主要讲述了数码相机MIPI接口协议说明，工作模式及信号传输原理等(Camera Interface Overview)

入门，verilog语言，实现字符型液晶1602的显示，及按键控制-verilog

数字秒表的实现，我还写个具体的过程要求等，(there is function of clock,it very useful)

PLL 锁相环verilog程序 可以直接使用(The PLL can be used directly good use)

详细讲述TURBO码的FPGA实现原理，可作参考，不是码源(A detailed account of the FPGA implementation of principle of the TURBO code can be used as reference, not source code)

把指定的噪声叠加到信号上去.有标准噪声库NOISEX-92，其中带有白噪声、办公室噪声、工厂噪声、汽车噪声、坦克噪声等等，在信号处理中往往需要把库中的噪声叠加到信号中去，而噪声的采样频率与纯信号的采样频率往往不一致，需要采样频率的校准。 (The specified noise superimposed to the signal up. Standard noise library NOISEX-92, with white noise, office noise, factory noise, car noise, tank noise in the signal processing often requires noise to be superimposed in the library The signal to noise of the sampling frequency and pure signal sampling frequency is often inconsistent sampling frequency of calibration.)

增强型8051的VHDL源代码，两个周期执行一条指令，仿真工具为Modelsim，开发板为Altera的EP1C20开发板-enhanced 8051 VHDL source code, the implementation of a two-cycle instruction, simulation tools for Modelsim, development board for the Altera EP1C20 development board